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It comes down to how full the bands are and how big the gap is. In copper the highest occupied band is only partly full, so roughly 10²³ electrons per cm³ have empty states right next to them and conduct at any temperature. In glass the valence band is full and the gap is about 9 eV, hundreds of times the 26 meV of thermal energy at room temperature, so essentially no electrons get across. Silicon also has a full valence band, but its gap is only 1.12 eV, so about 10¹⁰ electrons per cm³ are thermally excited at 300 K, and doping can then set its conductivity over many orders of magnitude.

From From atoms to energy bands · Semiconductors

Silicon is 1.12 eV, 4H silicon carbide is 3.26 eV and gallium nitride is 3.4 eV. A wider gap means far fewer thermally generated carriers, so leakage stays low at 175-200 °C, and the critical electric field is roughly ten times silicon's. That lets a 1200 V device use a drift layer about ten times thinner and much more heavily doped, which cuts on-resistance and switching loss. That is why 800 V traction inverters use SiC MOSFETs and compact USB-C chargers use GaN transistors.

From From atoms to energy bands · Semiconductors

Reverse leakage comes from thermally generated carriers, and the intrinsic carrier density goes as T^1.5 × exp(−Eg/2kT), so in silicon it roughly doubles every 10 °C. From 25 °C to 150 °C that is more than three orders of magnitude, so a 1 nA leak at room temperature becomes several microamps. I would keep every node that touches a junction at low impedance, budget leakage times impedance at the maximum temperature, and choose low-leakage clamps and CMOS- or JFET-input amplifiers characterized at 150 °C. For harsher jobs, such as downhole tools at 200 °C, I would move to SOI or SiC parts, where the buried oxide or the wider gap keeps leakage down.

From From atoms to energy bands · Semiconductors

Germanium came first, but its 0.66 eV gap makes it leaky above about 70 °C and its oxide dissolves in water, so it cannot protect or insulate a surface. Silicon grows a stable, high-quality SiO₂ simply by heating it in oxygen, and that native oxide made the planar process and the MOSFET possible around 1959-1960. Silicon is also abundant, about 28% of the Earth's crust, strong enough to be grown into 300 mm wafers, and its 1.12 eV gap keeps leakage manageable to about 150 °C. GaAs has roughly six times the electron mobility, but it has no usable native oxide and comes on smaller, costlier wafers, so it stays in RF amplifiers, lasers and LEDs.

From From atoms to energy bands · Semiconductors

In a direct-gap material such as GaAs or GaN, the bottom of the conduction band and the top of the valence band sit at the same crystal momentum, so an electron can fall across the gap and emit a photon on its own. In an indirect-gap material such as silicon, the electron must also trade momentum with a lattice vibration (a phonon), which makes light emission tens of thousands of times less likely. That is why LEDs and laser diodes use GaAs, InGaN and similar compounds. Silicon still absorbs light above its gap well enough to make good solar cells and camera sensors.

From From atoms to energy bands · Semiconductors

N-type silicon is doped with a group V element such as phosphorus or arsenic, whose fifth valence electron is freed at room temperature, so electrons are the majority carriers. P-type silicon is doped with a group III element, almost always boron, which leaves a bond short of an electron and creates a mobile hole, so holes are the majority. In both cases the dopant ion left behind is fixed in the lattice, positive for donors and negative for acceptors. Typical doping runs from about 10¹⁵ cm⁻³ in wafers up to 10²⁰ cm⁻³ in source and drain contacts.

From Doping, electrons and holes · Semiconductors

In equilibrium the product n times p equals n_i squared, about 10²⁰ cm⁻⁶ for silicon at 300 K. With n ≈ 10¹⁷ cm⁻³, p = 10²⁰ / 10¹⁷ = 10³ holes per cm³. The extra electrons recombine with most of the thermally generated holes, so the minority density falls as the majority density rises. Those few minority carriers still matter, because they carry leakage current and they are exactly what diodes and bipolar transistors inject.

From Doping, electrons and holes · Semiconductors

Drift is carrier motion driven by an electric field, with average velocity μE, and it dominates where majority carriers see an applied voltage, such as a resistor or the channel of a MOSFET in its linear region. Diffusion is motion down a concentration gradient, J = qD·dn/dx, and it dominates where minority carriers are injected into a region with almost no field, such as the base of a bipolar transistor. The two are linked by the Einstein relation D = μkT/q, so electrons, with about three times the mobility of holes, also diffuse about three times faster. In a p-n junction at equilibrium the drift and diffusion currents of each carrier cancel exactly, and that balance is what sets the built-in potential.

From Doping, electrons and holes · Semiconductors

An NMOS channel carries electrons and a PMOS channel carries holes, and in bulk silicon electron mobility is about 1400 against 450 cm²/V·s, roughly three times higher; in real inversion layers the ratio is closer to two or three. For the same width a PMOS delivers well under half the current, so it charges its load more slowly. Designers make PMOS devices two to three times wider to balance rise and fall times, and they prefer NAND gates, where the PMOS devices sit in parallel, over NOR gates, where they sit in series. Since Intel's 90 nm process in 2003, fabs have also strained the channel, using SiGe in the PMOS source and drain, to raise hole mobility.

From Doping, electrons and holes · Semiconductors

Sheet resistance is resistivity divided by layer thickness, quoted in ohms per square, because every square of a uniform thin layer has the same edge-to-edge resistance whatever its size. A resistor drawn in that layer is R_s times its length-to-width ratio, so a 10-square strip of a 280 Ω/□ layer is 2.8 kΩ. It is measured with a four-point probe: current is forced through the two outer needles and voltage is sensed across the two inner ones, which removes contact resistance from the reading. For a thin layer on a large wafer, R_s = 4.53 × V/I.

From Doping, electrons and holes · Semiconductors

The diode current is exponential, I = I_s(exp(V/nV_T) − 1), with V_T = 26 mV and I_s around 10⁻¹⁴ A for a small silicon junction. Solving for the voltage that gives milliamp currents lands between about 0.6 and 0.75 V, so on a linear plot the curve looks like it switches on near 0.7 V. It is not a threshold: the current changes tenfold for every 60 mV, and at 0.4 V tens of nanoamps already flow. The drop also falls about 2 mV per °C and grows with current through series resistance, which is why a 1N4007 shows about 1 V at 1 A.

From The p-n junction and diodes · Semiconductors

A Schottky is a metal-semiconductor junction that conducts with majority carriers only, so it has a lower forward drop, 0.2-0.4 V at modest current, and essentially no reverse-recovery charge. The price is much higher leakage that rises steeply with temperature, and lower voltage ratings, typically up to 100-200 V for silicon parts. I pick a Schottky for low-voltage rectification, switching-converter catch diodes and reverse-polarity protection where efficiency matters. I pick a PN diode where leakage must be low, the voltage is high, or cost matters more than the drop, such as a mains bridge rectifier.

From The p-n junction and diodes · Semiconductors

In forward conduction the junction has injected minority carriers, holes into the n side and electrons into the p side, stored as charge within a few diffusion lengths of the junction. When the voltage reverses, that stored charge must leave before the depletion region can widen and block, so a large reverse current flows for a while; this is reverse recovery, specified as trr and Qrr. A 1N4007 takes about 2 µs, which is fine at 50 Hz but turns into heat and ringing in a 100 kHz converter, where an ultrafast UF4007 at 75 ns or a Schottky with no stored charge is the right part. Once the charge is gone, the depletion region widens as the square root of the voltage, the junction capacitance falls, and only thermal leakage flows.

From The p-n junction and diodes · Semiconductors

A Zener is a diode designed to break down at a defined reverse voltage and survive it, as long as a resistor limits the current. Below about 5 V the junction is so heavily doped and the depletion region so thin, around 10 nm, that electrons tunnel straight across, and tunneling breakdown has a negative temperature coefficient. Above about 6-7 V the mechanism is avalanche multiplication, where the field accelerates carriers until they knock new electron-hole pairs loose, and that has a positive coefficient. Around 5.1-6.2 V the two effects cancel, so those parts drift least; for real precision I would still use a bandgap reference such as the TL431.

From The p-n junction and diodes · Semiconductors

An LED is a diode, so its current rises exponentially with voltage, and a few tens of millivolts can multiply it several times; driven straight from a supply it will overheat. The resistor sets the current: R = (V_supply − V_f) / I, so 5 V, a 2 V red LED and 10 mA give 300 Ω, and I would fit the standard 330 Ω for about 9 mA. I also check the resistor's power, here about 27 mW, and the LED's absolute maximum current. If the headroom is small, such as a 3 V blue LED on a 3.3 V rail, I use a constant-current driver, because the spread in V_f would swing the current wildly.

From The p-n junction and diodes · Semiconductors

An NMOS has n⁺ source and drain regions in a p-type body, with a gate electrode separated from the silicon by a thin oxide. With no gate voltage the path is two back-to-back p-n junctions, so no current flows. A positive gate voltage first pushes holes away from the surface and then pulls electrons in, and above the threshold voltage the surface inverts into a thin n-type channel connecting source and drain. Because the gate is insulated it draws essentially no DC current, so the MOSFET is controlled by voltage, not current.

From Transistors: BJT and MOSFET · Semiconductors

Below threshold the device is in cutoff, with only subthreshold leakage that falls about tenfold per 70-100 mV. With Vgs above threshold and Vds below the overdrive Vgs − Vth, it is in the triode or linear region and behaves like a resistor set by the gate. When Vds exceeds the overdrive, the channel pinches off at the drain and the current saturates at about ½μCox(W/L)(Vgs − Vth)². Switches should sit deep in the triode region with a low Rds(on), while amplifiers sit in saturation, where the gate voltage sets the current.

From Transistors: BJT and MOSFET · Semiconductors

I start with the gate drive I actually have, so I want a logic-level part with Rds(on) specified at 2.5 V and a Vgs(th) maximum well below that, such as 1-2 V. Then I size Vds at about twice the supply, so 30 V for a 12 V motor, and check the I²R loss: 2 A through 37 mΩ is 0.15 W, about 0.22 W hot, which a SOT-23 handles on a decent copper pad. I add a flyback diode across the motor, a small gate resistor and a 100 kΩ pull-down so the motor cannot twitch during reset. The classic mistake is a standard 10 V part driven at 3.3 V, which sits half on in the linear region and cooks; for fast PWM, gate charge and switching loss also start to matter, and a gate driver becomes worthwhile.

From Transistors: BJT and MOSFET · Semiconductors

A BJT is current-controlled, with Ic = βIb, and it needs base current the whole time it is on, while a MOSFET's insulated gate draws essentially no static current. That matters enormously for logic: a CMOS gate holding a state burns almost nothing, and MOSFETs scale geometrically, so Dennard scaling let each generation shrink dimensions and voltages together. NMOS and PMOS devices also sit side by side in one process, which makes CMOS possible. BJTs remain in precision analog circuits such as bandgap references, in RF as SiGe heterojunction transistors, and combined with a MOS gate as the IGBTs in many high-power inverters.

From Transistors: BJT and MOSFET · Semiconductors

In a vertical power MOSFET the p-body is shorted to the source to stop the parasitic bipolar transistor from turning on, and that leaves a p-n diode from source to drain. It conducts whenever the drain is pulled below the source, for example during dead time in an H-bridge, where it carries the inductive freewheeling current. It has a forward drop around 0.7-1 V and real reverse recovery, which adds switching loss, so synchronous designs turn the channel on to bypass it. It also means a single MOSFET cannot block current in both directions, which is why reverse-polarity and load-switch circuits often use two back to back.

From Transistors: BJT and MOSFET · Semiconductors

Every CMOS gate has a PMOS pull-up network to VDD and a complementary NMOS pull-down network to ground, driven by the same inputs. For any steady input combination exactly one network conducts, so there is never a DC path from supply to ground. Current flows only while the output switches, to charge or discharge the load capacitance, plus a brief short-circuit pulse while both networks are partly on. The static power that remains is leakage, which in modern nodes can still be a significant share of the total, especially when hot.

From CMOS logic: from gates to chips · Semiconductors

A two-input NAND has two NMOS in series from the output to ground and two PMOS in parallel from VDD to the output, so the output goes low only when both inputs are high. A NOR is the mirror image, with the PMOS in series and the NMOS in parallel. Series transistors add resistance, and PMOS devices are already two to three times weaker than NMOS because holes are less mobile, so a NOR needs very wide PMOS to match speeds. NAND puts the series stack on the faster NMOS side, and since NAND alone is functionally complete, standard-cell libraries lean on it.

From CMOS logic: from gates to chips · Semiconductors

Dynamic power is αCV²f, the cost of charging capacitance, plus a small short-circuit term, and static power is leakage, which rises steeply with temperature and with lower threshold voltages. The biggest lever is voltage because of the square, so DVFS lowers voltage and frequency together and adaptive voltage scaling trims each part to its own silicon. Clock gating stops the clock to idle blocks, cutting α, and power gating disconnects idle blocks entirely with header switches to remove their leakage. On top of that, designers use multi-threshold cell libraries, putting low-Vt fast cells only on critical paths and high-Vt low-leakage cells everywhere else.

From CMOS logic: from gates to chips · Semiconductors

SRAM stores a bit in two cross-coupled inverters with two access transistors, six transistors in all, so it is fast, about a nanosecond, and needs no refresh, but it is large, about 0.02 µm² per bit at the 3-5 nm nodes. DRAM uses one transistor and one capacitor per bit, which makes it several times denser and cheaper per bit, but the charge leaks, so every row is refreshed every 64 ms and access takes tens of nanoseconds. Flash stores charge on a floating gate or charge-trap layer, so it keeps data for years without power and stacks over 200 layers in 3D NAND, but reads take tens of microseconds, writes need 15-20 V tunneling and each cell survives only thousands of program-erase cycles. That is why a computer uses SRAM for caches, DRAM for main memory and Flash for storage.

From CMOS logic: from gates to chips · Semiconductors

Until the late 1990s a node name matched the gate length, but now it is a generation label: TSMC's 3 nm process has a contacted gate pitch around 45-50 nm and no feature that is 3 nm wide. The real story is density and electrostatics. A planar gate controls the channel only from the top, so below about 30 nm the drain's field leaked into the channel and the transistor could not turn fully off. FinFETs, from Intel's 22 nm process in 2011, wrap the gate around a thin fin on three sides, and gate-all-around nanosheets, from Samsung's 3 nm in 2022 and TSMC N2 and Intel 18A in 2025, wrap it on all four sides to keep leakage down as gates shrink further.

From CMOS logic: from gates to chips · Semiconductors

First you deposit or grow the film you want to pattern, then spin on photoresist and bake it. The scanner exposes the resist through a reticle, and in a positive resist the developer dissolves the exposed areas. A plasma etch transfers that opening into the film, then the resist is stripped and the wafer is cleaned and inspected. That loop, with implants, depositions and CMP in between, repeats for every mask layer, which is 60 or more times on a leading-edge chip.

From How chips are made: wafer fabrication · Semiconductors

DUV immersion uses 193 nm light from an ArF excimer laser, with water between the lens and the wafer to reach a numerical aperture of 1.35, which prints about 38-40 nm half-pitch in one exposure. Anything tighter needs multiple patterning, which adds masks, steps and overlay error. EUV uses 13.5 nm light made by hitting tin droplets with a CO2 laser, and because almost everything absorbs it, the optics are multilayer mirrors in vacuum. One EUV exposure can replace three or four DUV exposures on critical layers, which is why 7 nm-class nodes and below adopted it despite each scanner costing about $200 million.

From How chips are made: wafer fabrication · Semiconductors

FEOL, front end of line, builds the transistors in the silicon: isolation, wells, gate stack, source and drain. BEOL, back end of line, builds the copper wiring and low-k dielectric layers on top, often 10 to 15 or more levels. The split is mostly about thermal budget: once copper and low-k films are on the wafer, everything must stay below about 400 °C, so all high-temperature anneals must be finished in the FEOL. The two halves also use different tools and different engineering teams.

From How chips are made: wafer fabrication · Semiconductors

I would start with the Poisson model, Y = exp(−A·D0): a 1 cm² die at 0.1 defects per cm² yields about 90%, but a 6 cm² die at the same defect density yields only about 55%. To improve it, I can lower D0 by tracing defect sources with inline inspection and wafer-map signatures. I can make defects non-fatal with redundancy, such as spare SRAM rows and columns repaired by fuses. Or I can split the design into chiplets, test each small die, and assemble only known good dies, which is exactly why AMD moved its server CPUs to chiplets.

From How chips are made: wafer fabrication · Semiconductors

A lithography exposure only stays in focus over roughly 100 nm of height for immersion DUV, and less for EUV, so the wafer must be flat before every critical layer. CMP flattens oxide after trench isolation and removes the tungsten and copper overburden in damascene steps, leaving inlaid lines. Its failure modes are dishing of wide copper lines, erosion of dense arrays, scratches from slurry agglomerates or a badly conditioned pad, and leftover slurry particles. Designers help by following dummy-fill rules that keep metal density in a window, roughly 20% to 80%, so the polish removes material evenly.

From How chips are made: wafer fabrication · Semiconductors

Wire bonding connects pads on the edge of the die to the package with 15-50 µm gold or copper wires. It is cheap, mature and tolerant of die changes, but I/O is limited to the perimeter and each millimetre of wire adds about 1 nH of inductance. Flip chip turns the die face down onto an area array of bumps or copper pillars, so a big die can have thousands of short, low-inductance connections, and heat leaves through the back of the die into a lid. Most microcontrollers and analog parts are wire-bonded; CPUs, GPUs and high-speed networking chips are flip chip.

From Packaging and test · Semiconductors

The junction temperature is Ta + P·θJA = 50 + 1.5 × 40 = 110 °C. That is under a typical 125 °C limit, but with only 15 °C of margin, and θJA was measured on a JEDEC board that may have more copper than mine. I would check the copper area and thermal vias under the exposed pad, look for a package with lower θJA, or cut the dissipation, for example by replacing an LDO with a buck converter.

From Packaging and test · Semiconductors

A chiplet design splits one large chip into several smaller dies connected inside one package, such as AMD's EPYC with up to 12 CPU dies around one I/O die. Small dies yield far better because yield falls exponentially with area. Each function can use its best process, like CPU cores on 5 nm and I/O on 6 nm, and the total can exceed the 858 mm² reticle limit of a single die. The costs are die-to-die interface power and latency, harder packaging, and the need to test dies well enough that only known good dies get assembled.

From Packaging and test · Semiconductors

Silicon expands about 2.6 ppm/°C and an FR-4 board about 14-17 ppm/°C, so every temperature swing shears the joints that connect them. Each cycle adds a little plastic strain and a crack grows until the joint opens; the Coffin-Manson relation says life drops steeply as the temperature swing grows. Underfill locks the die to the substrate so flip-chip bumps share the strain, and larger balls, corner glue or compliant substrates help BGAs. Qualification runs something like 1,000 cycles from −55 °C to 125 °C and then cross-sections joints to look for crack growth.

From Packaging and test · Semiconductors

HBM stacks 8 to 12 or more DRAM dies with through-silicon vias and exposes a 1024-bit interface per stack, giving roughly 0.8-1.2 TB/s per stack. A bus that wide needs thousands of wires at tens of micrometres pitch, which only a silicon interposer or bridge can carry, not a normal organic substrate or PCB. So a GPU like NVIDIA's H100 sits beside its HBM stacks on a TSMC CoWoS interposer. In 2023 and 2024 that packaging capacity, not wafer capacity, was the bottleneck on AI accelerator supply.

From Packaging and test · Semiconductors

IGBTs make sense at high voltage and high current with modest switching frequency, such as 1,200 or 1,700 V industrial drives switching at 2-10 kHz. Their bipolar conduction gives an almost flat on-voltage of about 1.5-2 V even at hundreds of amps, and silicon IGBTs are cheap and rugged. MOSFETs, especially SiC, win when you need higher frequency or better light-load efficiency, because they have no knee voltage and no tail current. In a 400 V EV inverter both work, which is why the choice there often comes down to cost.

From Power semiconductors: Si, SiC and GaN · Semiconductors

Conduction loss is I²·R = 100² × 0.010 = 100 W. Switching loss is Esw·f = 1 mJ × 10,000 per second = 10 W, so 110 W in total. If the die runs at 150 °C, Rds(on) can be about 40% higher, which makes conduction 140 W. That is why I always read Rds(on) and Esw at the real junction temperature, not the 25 °C headline value.

From Power semiconductors: Si, SiC and GaN · Semiconductors

The Model 3, launched in 2017, was the first high-volume car with SiC MOSFETs in its main traction inverter, using 24 SiC modules from STMicroelectronics. SiC has no knee voltage, so at the light loads where a car spends most of its time it loses far less than an IGBT, which is commonly credited with several percent more range and less cooling. It also tolerates higher junction temperatures. The trade-offs were a more expensive device and more care with gate drive and EMI.

From Power semiconductors: Si, SiC and GaN · Semiconductors

The critical electric field rises steeply with band gap: about 0.3 MV/cm for silicon and about 2.5-3 MV/cm for 4H-SiC. The drift region needs a width of roughly 2V/Ec to block a voltage, so SiC needs about a tenth of the thickness, and it can be doped about 100× more heavily. Drift resistance goes as W/(qμN), so the ideal specific on-resistance at 1,200 V is several hundred times lower than silicon's. That is why a 1,200 V SiC device can be a fast, unipolar MOSFET, while silicon needs an IGBT with conductivity modulation and a tail current.

From Power semiconductors: Si, SiC and GaN · Semiconductors

GaN switches in a few nanoseconds, so a few nanohenries in the power loop or gate loop cause big overshoot and ringing. GaN's threshold is low, around 1-1.7 V, so Miller current from a fast dv/dt through Cgd can lift the gate of the off device and cause shoot-through. I would shrink the power loop with tight bypass capacitors, use a Kelvin-source gate return and separate turn-on and turn-off resistors, and hold the off-state gate firmly at or below zero. Then I would remeasure with a high-bandwidth probe and a short ground spring, because a long ground lead creates ringing that is not really there.

From Power semiconductors: Si, SiC and GaN · Semiconductors

A fabless company, such as NVIDIA or Qualcomm, designs chips and owns the customer but pays a foundry to make them. A foundry, such as TSMC, manufactures wafers for many customers and does not sell its own chip designs. An IDM, such as Texas Instruments or Infineon, does both: it designs, fabricates and usually tests its own products. The lines are blurring: Intel now runs Intel Foundry for outside customers, and TSMC does advanced packaging that used to be OSAT work.

From The industry map and the jobs · Semiconductors

An applications engineer is the bridge between a chip and the customers designing it into products. Day to day that means writing reference designs and application notes, answering design questions, reviewing customer schematics and layouts, and debugging boards in the lab when something does not work. They also carry customer requirements and failure reports back to the product and design teams. It suits someone who likes hands-on hardware debug as much as explaining things clearly.

From The industry map and the jobs · Semiconductors

ASML is the only company that makes EUV lithography scanners, which every chip at 7 nm-class and below depends on, and each costs around $200 million. TSMC manufactures most of the world's leading-edge logic, including chips for Apple, NVIDIA, AMD and Qualcomm. That concentration means export controls on ASML tools, or any disruption in Taiwan, touches almost every advanced product. It is also why the CHIPS Act paid to build leading-edge fabs in the United States.

From The industry map and the jobs · Semiconductors

First I would gather data and contain: failure rate in ppm, lot and date codes, the application and mission profile, and the failure signature, and I would hold suspect inventory. Then I would verify the failure on returned parts at the field condition, for example a hot test at 125 °C, next to known good parts. Next come non-destructive steps such as X-ray and acoustic microscopy, then electrical fault isolation with curve tracing and thermal or emission imaging, and only then decapsulation and cross-sections to find the physical defect. Finally I would document root cause, corrective action and verification tests in an 8D report, and check whether other products share the same risk.

From The industry map and the jobs · Semiconductors

Gordon Moore observed in 1965 that component counts were doubling every year, and in 1975 revised it to about every two years, which held for decades: the Intel 4004 had 2,300 transistors in 1971 and Apple's M1 had 16 billion in 2020. Dennard scaling, which kept power density constant as transistors shrank, ended around 2005, so clock speeds stalled near 3-5 GHz. Progress now comes from new transistor structures like FinFET and gate-all-around, EUV lithography, specialised accelerators, and advanced packaging with chiplets and HBM. Node names such as 3 nm are now labels rather than any physical dimension.

From The industry map and the jobs · Semiconductors

I start with the ratio: 3.3 / 12 = 0.275, so R1 / R2 = 2.64. I pick R2 = 10 kΩ so the divider draws well under a milliamp, which makes R1 = 26.4 kΩ, and I use the nearest standard value, 27 kΩ, for 3.24 V out at 324 µA. Then I check loading: the output resistance is R1 in parallel with R2, 7.3 kΩ, so the ADC or a filter capacitor must not disturb it by more than a percent or two. Finally I design for the worst case rather than the nominal one: a 12 V lead-acid battery reaches 14.4 V while charging, which would put 3.9 V on a 3.3 V pin, so I would move to 36 kΩ and 10 kΩ and add a 100 nF capacitor at the pin.

From Circuit fundamentals you actually use · PCB Design

KCL says the currents entering a node sum to zero, because charge cannot pile up at a point. I use it to find a branch current, for example when a load taps off a divider. KVL says the voltage rises and drops around any closed loop sum to zero, because voltage is a potential difference. I use it to find an unknown voltage, such as how much of a 12 V supply is left after two series resistors. Together with Ohm's law they solve any resistor network, and I use them as sanity checks: if the drops around a loop do not add up to the source, my schematic or my measurement is wrong.

From Circuit fundamentals you actually use · PCB Design

Current is measured in series: I break the circuit, move the red lead to the mA or A jack and put the meter in the path so the current flows through it. In that mode the meter is a near-zero resistance, a few ohms or less. The classic mistake is leaving the leads in the current jacks and then probing a voltage across a supply, which is almost a short circuit and blows the meter fuse. I move the lead back to the voltage jack right after each current measurement, and on small boards I often measure the voltage across a known shunt resistor instead.

From Circuit fundamentals you actually use · PCB Design

A floating CMOS input has no defined voltage, so it drifts wherever stray capacitance and leakage push it, and it picks up mains hum and nearby switching noise. Near the middle of the logic range both input transistors conduct, so it can draw extra current and read as random zeros and ones. The fix is to give it a defined state with a pull-up or pull-down resistor, typically 10 kΩ, or an internal pull of roughly 30 to 50 kΩ when the timing allows. Enable, reset, strap and unused gate inputs all deserve the same discipline, because a floating pin can work on the bench and fail in the field.

From Circuit fundamentals you actually use · PCB Design

Any linear two-terminal network behaves like one ideal source in series with one resistor. For a divider the source is the unloaded output, Vin · R2 / (R1 + R2), and the series resistance is R1 in parallel with R2, so 27 kΩ and 10 kΩ give 3.24 V behind 7.3 kΩ. A load RL forms a second divider with that Thevenin resistance, so the output falls by the factor RL / (RL + Rth). A 10 kΩ load drags 3.24 V down to 1.88 V, while a 1 MΩ load costs only 0.7%. The rule of thumb is a load of at least 10 times Rth for about 10% error and 100 times for about 1%, which is why dividers feed high-impedance inputs and why I add a buffer or a capacitor in front of a sampled ADC.

From Circuit fundamentals you actually use · PCB Design

The time constant is 10 kΩ × 100 nF = 1 ms, so the cutoff is 1 / (2π · 1 ms) = 159 Hz and 1 kHz sits well above it. Each half period is 0.5 ms, only half a time constant, so the capacitor never gets near either rail. The output settles into a roughly triangular wave centred on 1.65 V that swings between about 1.25 V and 2.05 V, around 0.8 V peak to peak instead of 3.3 V. If I drop the frequency below roughly 50 Hz the output looks like the input again, and if I raise it to 10 kHz the ripple shrinks to about 80 mV.

From Circuit fundamentals you actually use · PCB Design

I put one 100 nF X7R capacitor in an 0402 or 0603 on every supply pin, as close to the pin as the footprint allows, with the ground via right at the capacitor pad. Then I add a bulk capacitor of 4.7 to 10 µF per rail, nearer the regulator, to cover slower load steps. I pick a voltage rating of 2 to 3 times the rail because X7R loses capacitance under bias, so a 10 µF, 6.3 V part on 3.3 V may only be 6 µF. For an analog supply such as VDDA I add 1 µF behind a ferrite bead or a small resistor to keep digital noise out.

From Passives: resistors, capacitors, inductors · PCB Design

They are dielectric classes. C0G, also called NP0, is Class I: ±30 ppm/°C, no change with DC bias and almost no aging, but limited to roughly 100 nF in an 0805. X7R is Class II: ±15% from −55 to +125 °C and far more capacitance per volume, but it loses 40% or more under DC bias and shows some aging and microphonic effects. Y5V swings +22/−82% over temperature and loses even more under bias, so I avoid it for anything that matters. In practice I use C0G for timing and RF, X7R for decoupling and bulk, and Y5V almost never.

From Passives: resistors, capacitors, inductors · PCB Design

Two things. First, 5 V is 79% of the rating, which leaves no margin for ripple, spikes or aging, and ceramics can crack or degrade when run near their limit. Second, DC-bias derating: at 5 V a 10 µF, 6.3 V part in an 0603 can deliver less than half of its marked capacitance, so the rail has far less bulk capacitance than the schematic claims. I would move to a 16 V or 25 V part, maybe a larger case, and read the manufacturer's bias curve for the real capacitance at 5 V.

From Passives: resistors, capacitors, inductors · PCB Design

ESR is the equivalent series resistance of a capacitor, the small resistance in series with its ideal capacitance. It turns ripple current into heat, P = I² · ESR, so it sets the ripple rating of an electrolytic, and together with the capacitance it sets the output ripple of a switching regulator. For some older LDOs, the AMS1117 among them, it matters in the other direction, because the control loop expects some ESR in the output capacitor and a very low-ESR ceramic can make it oscillate. As a rule, ceramics are tens of milliohms, polymers a few tens of milliohms, and aluminium electrolytics a few hundred milliohms to ohms.

From Passives: resistors, capacitors, inductors · PCB Design

Above its saturation current the core can hold no more flux, so the inductance collapses, usually defined as a 20 to 30% drop, and the current ramps almost unchecked until something else limits it. In a buck converter that sends a current spike through the switch, which can trip the current limit or destroy the FET. I choose L from the ripple target, ΔI = (Vin − Vout) · D / (L · f), usually 20 to 40% of the load current. Then I pick a part whose saturation current is above the converter's current limit with margin and whose RMS rating covers the load, and I check that DCR keeps the I² · R loss and heating acceptable.

From Passives: resistors, capacitors, inductors · PCB Design

Every real capacitor is a series RLC: the capacitance, its ESR, and an equivalent series inductance of about 0.5 to 1 nH for an 0402 plus a nanohenry or so from the pads and vias. At the self-resonant frequency, f = 1 / (2π√(LC)), the reactances cancel and the impedance is just the ESR, and above it the part behaves like an inductor. 100 nF with 1 nH resonates near 16 MHz and 10 µF with 2 nH near 1.1 MHz, so each value covers a different band. Mixed values can create anti-resonance peaks between them, so I use a few well-chosen values placed close to the pins instead of a pile of different ones.

From Passives: resistors, capacitors, inductors · PCB Design

I decide with numbers. An LDO loses (Vin − Vout) × I as heat and has an efficiency of Vout / Vin, so 12 V to 3.3 V at 500 mA wastes 4.35 W, while a buck at about 90% wastes under 0.2 W. An LDO wins when the dropout is small, the current is low, noise matters or space is tight: it needs one or two capacitors, has no switching ripple, and gives 60 dB or more of supply rejection. A buck wins whenever the voltage drop or the current is large, because efficiency, heat and battery life then dominate. A common answer is both: a buck brings the rail close to the target and a low-noise LDO cleans it up for ADCs and sensors.

From Active components: regulators, op-amps, MCUs · PCB Design

With negative feedback the output moves until the two inputs are at the same voltage, and the inputs themselves draw no current. In an inverting amplifier the non-inverting input is grounded, so the inverting input sits at 0 V, a virtual ground. The input current is Vin / Rin and, because none of it enters the op-amp, all of it flows through Rf, which gives Vout = −Vin × Rf / Rin. For example Rf = 100 kΩ and Rin = 10 kΩ give a gain of −10. The same two rules give 1 + Rf / Rg for the non-inverting amplifier.

From Active components: regulators, op-amps, MCUs · PCB Design

First, clean power: a 100 nF capacitor at every supply pin plus a bulk capacitor, and a filtered supply for the analog pins. Second, a defined reset and boot configuration, for example a 10 kΩ pull-up on the reset or EN pin, often with a capacitor and a button to ground, and the correct level on the boot-mode strap pins. Third, a clock: many MCUs run from an internal oscillator, but USB, CAN and accurate timing need a crystal with the right load capacitors. Finally, a way in: a programming and debug header such as SWD with SWDIO, SWCLK, reset, 3V3 and ground, or a USB-UART bridge with auto-reset.

From Active components: regulators, op-amps, MCUs · PCB Design

It depends on direction and speed. For a slow one-way signal such as the HC-SR04 echo, a resistor divider like 1 kΩ over 2 kΩ turns 5 V into 3.3 V for two cheap parts. For a bidirectional bus such as I²C I use a MOSFET level shifter, a BSS138 per line with pull-ups on both sides, or a dedicated translator. For fast push-pull signals I use a buffer such as a 74LVC245 powered at 3.3 V. Before any of that I check whether the MCU pin is 5 V tolerant, and many are not, including the ESP32.

From Active components: regulators, op-amps, MCUs · PCB Design

In continuous conduction the ideal duty cycle is Vout / Vin = 3.3 / 12 = 27.5%. The inductor current ramps by (Vin − Vout) × D / (L × f) over the on-time, so L sets the ripple current, and I usually target 20 to 40% of the load current. For 0.5 A at 500 kHz that is about 0.15 A, so L = 8.7 V × 0.275 / (0.15 A × 500 kHz) = 32 µH and I would pick 33 µH. The output ripple voltage is roughly ΔI / (8 × f × Cout), which is 1.7 mV for 22 µF, plus ΔI × ESR. Finally I check that the saturation current exceeds the peak, Iload + ΔI / 2, with margin.

From Active components: regulators, op-amps, MCUs · PCB Design

The switching edges carry amps in nanoseconds, so any loop inductance turns into voltage spikes and radiated noise. The most critical is the hot loop: input capacitor, high-side switch and low-side switch back to the input capacitor. I make it as small as possible with the capacitor right at the IC pins on the same layer. Next is the switch node, which swings the full input voltage with fast edges, so I keep its copper as small as the inductor pad allows and keep the feedback divider and other sensitive traces away from it. I give the converter an unbroken ground plane, take the feedback trace from the output capacitor, and follow the datasheet's reference layout.

From Active components: regulators, op-amps, MCUs · PCB Design

The pack reaches J1 and Q1's gate is held at ground by R1, so the P-FET turns on and VM rises through its 50 mΩ channel. The bulk capacitors charge, the AMS1117 brings 3V3 up, and the driver stays idle because its STBY pin is pulled low. EN rises through R2 into C8 with a 10 ms time constant, so the ESP32 is released about 14 ms after the rail, once it is stable. The firmware then sets the pins, enables STBY, and the H-bridges start steering current into the windings. Every step is a law in action: Ohm at Q1, Kirchhoff at the VM node, RC on EN.

From Components in action: one board, every law · PCB Design

At the VM node, where the pack current splits into the two motor channels and the regulator. Whatever each branch draws, the sum comes through the connector, the fuse, Q1 and the first stretch of trace, so those parts are rated for the sum, not for one branch. Two stalled N20 motors are about 3 A together, which is why the JST XH pins, a 3 A fuse and a 1.5 mm trace were chosen. If I later add a branch, say a 5 V buck for a servo, the same node tells me the connector budget just shrank.

From Components in action: one board, every law · PCB Design

An LED is a diode: above its forward voltage the current rises very steeply, so without a resistor the pin or the LED would set the current by accident. Kirchhoff's voltage law around the loop gives 3.3 V = I · R + Vf, so R = (3.3 − Vf) / I. For a red LED at 2.0 V and 1.3 mA that is 1 kΩ, and the resistor dissipates only 1.7 mW. A blue LED drops about 3.0 V, which leaves 0.3 V for the resistor and barely 0.3 mA through 1 kΩ, so it needs about 60 Ω for 5 mA or a higher supply. I also keep the current well under the 20 mA a GPIO pin can source.

From Components in action: one board, every law · PCB Design

Point the thumb of your right hand along the current in a wire and your fingers curl the way the magnetic field circles it; for a coil, curl the fingers along the current and the thumb points along the field inside, toward the coil's north end. In the motor, the H-bridge sets which way the current flows through the winding, so reversing AIN1 and AIN2 reverses the field and the torque. The same rule explains why the motor traces radiate: the current loop from the driver to the connector and back makes a field proportional to its area, which is why the loop is kept short and over a ground plane.

From Components in action: one board, every law · PCB Design

The heat is (Vin − Vout) · I plus the ground current's share: 5.1 V × 0.15 A is 0.77 W, plus 8.4 V × 5 mA, about 0.81 W in total. At 60 °C/W for a SOT-223 on a modest pad that is a 48 °C rise, so about 73 °C in a 25 °C room, which is fine. The budget runs out near 400 mA, where 2.1 W puts the junction at the 150 °C shutdown line, and sooner in a warm enclosure. I would switch to a buck, or add one as a pre-regulator, once the sustained current passes about 250 mA, because the junction would then sit above 100 °C and Wi-Fi bursts would push it further. A buck at 90% efficiency wastes about a tenth of that power.

From Components in action: one board, every law · PCB Design

Seen from the pin, the divider is a source of Vpack × 47 / 147 behind R1 ∥ R2 = 32 kΩ. A successive-approximation ADC connects a small sampling capacitor to the pin for a short window, and through 32 kΩ that capacitor cannot reach the source voltage before the conversion starts, so the result reads low, and it depends on whatever the previous channel left on the capacitor, which is the noise. The fix is a 100 nF capacitor from the pin to ground: it holds thousands of times the sampling charge, so each sample takes a negligible bite, and the divider refills it with a 3.2 ms time constant between readings. Smaller resistors, 10 kΩ over 4.7 kΩ, would also work but would draw 0.57 mA from the pack all the time. I would also average a few samples in firmware and check the ESP32's attenuation setting.

From Components in action: one board, every law · PCB Design

An electrical rules check analyses connectivity against a pin-type matrix. It finds unconnected pins, power inputs that no power output drives, two outputs wired together, duplicate reference designators, labels that join only one pin, and sheet-pin mismatches. It cannot know your intent, so a missing pull-up, a wrong resistor value, a mirrored connector pinout or a regulator that cannot supply the load all pass cleanly. I treat a clean ERC as the minimum bar, then review the design pin by pin against the datasheets, and I either fix every message or write down why it is waived.

From Schematic capture: drawing a circuit people can read · PCB Design

I follow signal flow, with inputs on the left and outputs on the right, positive supplies at the top and grounds at the bottom, and I never draw a ground symbol pointing up. Each page covers one function, and I split large designs into hierarchical sheets such as power, MCU and motor driver. Nets get meaningful names like MOTA_PWM instead of auto-generated ones, and decoupling capacitors are drawn right next to the IC pin they serve. Every part carries a reference designator, a value with the critical specs, and a footprint, and I add short notes for non-obvious choices such as why a pull-down is 100 kΩ.

From Schematic capture: drawing a circuit people can read · PCB Design

A useful BOM groups identical parts and lists reference designators, quantity, value, footprint, manufacturer, manufacturer part number and a supplier part number, plus flags for parts that are not populated. A value such as 100 nF does not say the dielectric, voltage rating or package, and those decide whether the part works, so the MPN and a full description are the ground truth. I also list approved alternates, check stock and lifecycle status, and confirm that alternates are footprint compatible. A clean BOM lets the assembler order and place everything without calling me.

From Schematic capture: drawing a circuit people can read · PCB Design

A local label joins nets of the same name within one sheet only. A global label joins every net of that name across all sheets, which is convenient but harder to trace on a large project. A hierarchical label ties a net to a pin on the sheet symbol in the parent page, so connections between sheets are explicit. Power symbols such as +3V3 and GND behave like global labels for supplies, so I never draw supply wires by hand. The risk with any label is a typo, which silently makes two separate nets, and ERC reports it only as a single-pin-net warning.

From Schematic capture: drawing a circuit people can read · PCB Design

I start with power: I list every rail, what produces it and the worst-case load, and check each regulator for dropout, dissipation and capacitor requirements. Then I go through every IC pin by pin against the datasheet and its reference design, checking that each input has a defined state, unused pins are handled, strap and boot pins are at the right level and absolute maximum ratings are respected. I check interfaces for level compatibility, pull-ups on open-drain buses and protection at connectors, and I confirm that connector pinouts are not mirrored. Finally I check decoupling, footprints against the land patterns, test points and the BOM, and I confirm the ERC log has no unexplained messages.

From Schematic capture: drawing a circuit people can read · PCB Design

A 4-layer stack of signal, ground, power and signal gives every signal a solid, unbroken ground plane next to it, which shrinks the loop area of every current and lowers EMI and crosstalk. It also makes power distribution easier, because a plane or large pour feeds the whole board at low impedance. With about 0.2 mm of prepreg between the top layer and the ground plane, a 0.35 mm trace becomes a 50 Ω line, which a 2-layer board with a 1.5 mm gap cannot do without a trace about 3 mm wide. The cost is a prototype that is several times more expensive and a stack-up you must specify, so I use 2 layers for simple low-speed boards and move to 4 once there is an MCU with fast edges, USB or a noisy motor driver next to analog.

From PCB layout and stack-up · PCB Design

I use IPC-2221, or IPC-2152 when accuracy matters, starting from a temperature-rise budget of 10 to 20 °C. For 3 A, a 10 °C rise and 1 oz copper on an outer layer the width is about 54 mil, 1.4 mm, and an inner layer needs about 2.6 times that. Going to 2 oz copper halves the width, and a copper pour is better still because it spreads the heat and costs no routing effort. Then I check the voltage drop, which for 50 mm of 1.4 mm trace is only about 18 mΩ, and the vias, since a 0.3 mm via carries on the order of 1 A, so a layer change needs several in parallel.

From PCB layout and stack-up · PCB Design

A through via is drilled through the whole board and plated, the cheapest option and the default. A blind via joins an outer layer to one or more inner layers without reaching the other face, and a buried via joins inner layers only, so neither shows on both sides. A microvia is laser-drilled, about 0.1 mm across, and spans a single dielectric layer, which is how high-density boards escape fine-pitch BGAs. Blind, buried and micro vias need sequential lamination and cost much more, so I stay with through vias at a 0.3 mm drill and 0.6 mm pad unless pitch or density forces a change.

From PCB layout and stack-up · PCB Design

HASL coats the pads with molten solder and levels them with hot air. It is cheap and robust, but the surface is uneven, which hurts fine-pitch parts below about 0.5 mm and BGAs. ENIG plates 3 to 6 µm of electroless nickel under a thin immersion gold flash of 0.05 to 0.1 µm, which is flat, keeps well on the shelf and suits fine pitch, at a higher cost and with a small risk of black-pad defects. For a prototype robot board with 0.65 mm pitch parts, lead-free HASL is usually fine, and I choose ENIG for fine pitch, BGAs or anything that needs flat pads.

From PCB layout and stack-up · PCB Design

I start with the constraints: the board outline, mounting holes, connectors and keep-outs such as the antenna area. Then I place the power entry and the driver near the motor connectors so the high-current loops are short, the regulator close to the battery input, and the MCU with its decoupling capacitors at the pins, keeping analog and sensor parts on the far side from the noisy switching nodes. I route power and ground first with wide traces or pours, then the sensitive signals such as clocks and ADC inputs, then the rest, keeping signals over an unbroken plane. I finish with ground and power fills, stitching vias, silkscreen and a DRC pass, and then review the current loops and thermal paths once more.

From PCB layout and stack-up · PCB Design

Thermal relief connects a pad to a copper pour through a few narrow spokes, typically four spokes 0.25 to 0.3 mm wide. During soldering the pad then heats up quickly instead of dumping its heat into the whole pour, which prevents cold joints and tombstoning of small passives. The spokes add electrical and thermal resistance, so I switch relief off or use wide spokes on pads that carry high current, such as motor-driver supply pins and connectors. Under a QFN exposed pad, where heat has to leave the package, I use a solid connection with thermal vias, so I decide each case by asking whether the pad needs to solder easily or to conduct well.

From PCB layout and stack-up · PCB Design

Every signal is a loop: current goes out along the trace and has to come back to its source. At low frequency it takes the least-resistance path and spreads through the copper, but above roughly 100 kHz it takes the least-inductance path, which is directly under the trace on the adjacent plane. The area between the signal and its return is the loop area, and both radiated emissions and noise pickup scale with it. So good layout is mostly about keeping a continuous reference plane under every fast trace.

From Power integrity, signal integrity and EMI · PCB Design

As close to the power pin as the footprints allow, with the ground via right at the capacitor pad and the power trace passing the capacitor before it reaches the pin. The capacitor only works while it looks like a capacitor, and the loop inductance sets its self-resonance: 100 nF with 1 nH resonates near 16 MHz, but with 10 nH only near 5 MHz. Above that it is an inductor and the voltage spike is simply L times di/dt. I use a 0402 or 0603 part, one per power pin, and put the smallest value nearest the pin.

From Power integrity, signal integrity and EMI · PCB Design

The return current cannot cross the gap, so it detours around the end of the slot. That enlarges the loop, adds inductance, couples noise into everything near the detour and raises radiated emissions. The first fix is to avoid the split, by rerouting the signal or removing the cut. If it must cross, I put a stitching capacitor, typically 100 nF, within a few millimetres of the crossing so the fast return current can hop the gap, and I keep the trace on a layer whose reference is continuous.

From Power integrity, signal integrity and EMI · PCB Design

When its one-way delay is more than roughly one-sixth of the signal's rise time. FR-4 outer layers delay a signal by about 6 ps per millimetre, so the critical length is about 28 mm per nanosecond of rise time. A 1 ns edge makes a trace over 28 mm a transmission line even if the clock is only 1 MHz, because the edge rate sets the bandwidth, not the clock. Past that length I control the impedance, usually 50 Ω, and terminate the line to stop reflections.

From Power integrity, signal integrity and EMI · PCB Design

I look at the rails first, with a scope triggered on a dip of the 3V3 rail and the probe ground spring on the module's own ground pin, then compare it with VM at the motor driver. If VM sags, the motor inrush is being pulled through the battery lead without local bulk capacitance, and I add 100 µF plus ceramics at the driver. I also check where the motor return current flows; if it shares a trace with the logic ground, I give it its own path back to the battery. Finally I check the regulator's dropout, soft-start the PWM and re-measure under the same start-up.

From Power integrity, signal integrity and EMI · PCB Design

Partition by placement: motor driver, bulk capacitor and battery connector in one corner so the motor current returns straight to the battery, and the ADC inputs far from that loop. I keep one solid ground plane rather than splitting it, so the return current under every analog trace stays continuous. Each analog input gets an RC filter, for example 1 kΩ and 100 nF, the traces stay away from switching edges, and I filter motors at the source with 100 nF across the terminals. In firmware I sample between PWM edges and average several readings.

From Power integrity, signal integrity and EMI · PCB Design

DRC checks the layout against rules you or the fab set in the CAD tool: clearance, track width, drill size, annular ring and courtyards. It is geometry against numbers. DFM asks whether a factory can build the board reliably and cheaply, so it also considers process effects such as acid traps, mask slivers, thermal balance of pads, paste volume, fiducials and panelisation. A board can pass DRC and still tombstone or come back with opens. I put the fab's capability sheet into the DRC rules first, then run the fab's own DFM check before paying.

From DFM and how boards get made · PCB Design

The fab needs Gerber RS-274X files for each copper layer, solder mask, silkscreen, paste and the board outline, plus an Excellon drill file; some fabs accept a single IPC-2581 or ODB++ package instead. For assembly I add a bill of materials with manufacturer or supplier part numbers, a centroid file listing each reference designator's X, Y, rotation and side, and an assembly drawing with polarity marks. I open the Gerbers in a viewer before uploading, and I check the assembler's placement preview for rotation errors on polarised parts.

From DFM and how boards get made · PCB Design

Preheat brings the board up at no more than about 3 °C/s to 150 °C so the parts are not shocked. The soak from 150 to about 200 °C over 60 to 120 seconds activates the flux and evens out temperature between large and small parts. Then the board ramps through the 217 °C liquidus of SAC305 to a peak around 245 °C and spends 45 to 90 seconds above liquidus, long enough to wet but short enough to protect parts and limit intermetallic growth. Too cool or too short gives dull cold joints and poor wetting, while too hot or too long damages components and the laminate. Cooling quickly but no faster than about 6 °C/s, which would shock the parts, gives a fine-grained joint, while a very slow cool coarsens the grain and thickens the brittle intermetallic layer.

From DFM and how boards get made · PCB Design

Tombstoning is when a small chip, usually 0402 or smaller, stands on one end after reflow. It happens when the solder on one pad melts before the other, so surface tension pulls that end down and lifts the far end. The usual causes are unequal thermal mass between the pads, such as one pad on a pour, unequal pad size or paste volume, and a fast ramp. I prevent it with symmetric pads, thermal relief on any pad tied to a pour, balanced stencil apertures and a slower ramp with a soak.

From DFM and how boards get made · PCB Design

I start from the fab's capability page and pick the cheapest tier that fits, because tighter rules cost money and yield. My defaults are 0.2 mm track and space and a 0.3 mm drill with a 0.6 mm via pad, and I drop to the fab's minimum only locally, for example escaping a fine-pitch QFN. I leave 20 to 30 % margin over the minimum so normal process variation does not turn into scrap. Then I enter those numbers as design rules in the CAD tool so DRC enforces them while I route, and I confirm with the fab's DFM check before ordering.

From DFM and how boards get made · PCB Design

It means treating manufacturability as a compiler pass instead of a review at the end. An AI system proposes geometry or a layout, and an automated checker applies the fab's rules, such as minimum wall thickness, drill sizes, clearances and bend radii. The violations go back to the generator as errors, and the loop runs until the design compiles with zero violations. For a PCB the same idea is a CI job that runs DRC with the fab's rules on every commit and fails the build on any violation. It moves the discovery of a 0.1 mm sliver from after the order to before a human ever sees the draft.

From DFM and how boards get made · PCB Design

I inspect it under magnification for polarity, pin 1 orientation, solder bridges and missing parts, comparing every polarised part with the assembler's placement preview. Then, with power off, I measure the resistance from each supply rail to ground and from rail to rail; a reading near zero means a short and I stop there. Only after that do I connect a bench supply set to the right voltage with the current limit just above the expected idle current, with motors and loads unplugged. I raise the voltage from zero and watch the current as I go.

From Board bring-up and debugging · PCB Design

I need enough bandwidth, since a scope's rise time is about 0.35 divided by its bandwidth and it will round off any edge near that speed. I use a 10x probe with a short spring ground tip touching a ground pad beside the signal pad instead of the long clip lead. A 15 cm clip adds about 150 nH, which with the probe's 10 pF rings near 130 MHz and picks up magnetic noise through its large loop. I also check the probe's compensation first, and I never clip the ground to a node that is not at ground.

From Board bring-up and debugging · PCB Design

I stop at once, because the current limit has done its job. Power off, I check the resistance of each rail to ground to see which rail is shorted. Then I inject current straight into that rail, about 1 V at 0.5 A, so the regulator is out of the picture, and look with a thermal camera for the part that warms up. A reversed capacitor, a reversed IC or a damaged part will glow, but a dead short makes almost no heat, so for those I measure millivolts along the rail and follow the voltage down to the short. I confirm by removing the suspect and re-measuring.

From Board bring-up and debugging · PCB Design

When the question is what bits were sent, not what the signal looked like. A logic analyzer captures eight or sixteen digital channels at once and decodes I2C, SPI and UART, so I can see an address byte, a missing acknowledge or a wrong clock polarity over thousands of transactions. It will not show ringing, slow edges or low levels, so when a bus misbehaves I use the analyzer to see the traffic and then the scope to check the electrical quality of one line. I sample at least four times faster than the bus clock and set the threshold for the logic level.

From Board bring-up and debugging · PCB Design

I make the fault repeatable first, for example by triggering a single-shot scope capture on the rail dip. Then I bisect: measure a node in the middle of the system, decide which half holds the fault, and repeat. I change one variable at a time and write down every reading, the board serial and the setup, because intermittent faults hide in what I forgot I changed. If I have a known-good board I compare the same node on both, and I only declare it fixed after the original condition fails to reproduce several times.

From Board bring-up and debugging · PCB Design

On a moulded SMD tantalum the stripe or bevelled end marks the positive terminal. On an aluminium electrolytic can the stripe or dark band marks the negative terminal, which is the opposite convention. On a diode the band marks the cathode. I do not rely on memory for a new part: I check the datasheet marking drawing and the footprint's silkscreen, because a tantalum fitted backwards can fail short and burn.

From Board bring-up and debugging · PCB Design

I start with the schematic: place symbols, connect or label the nets, add power flags, annotate and run ERC until it is clean. Then I assign footprints, check each against the datasheet's land pattern and push everything to the board with Update PCB from Schematic. In the board editor I set the stack-up and design rules from the fab's capability sheet, draw the outline, place parts by zone, route power first and then signals, fill the ground zones and run DRC to zero errors. Finally I plot Gerbers and drills, export the position file and BOM, check them in a viewer and submit them to the fab's DFM check.

From Practical: design the robot's motor-driver board in KiCad · PCB Design

ERC runs on the schematic and checks electrical consistency: unconnected pins, outputs driving each other, power inputs with no source and missing flags. DRC runs on the board and checks copper clearances, track widths, drill sizes, annular rings, copper-to-edge distance and zone connectivity against the rules you set. Neither knows whether the circuit works, whether a footprint matches the real part, or whether the board fits its enclosure. Those need a design review, a datasheet check and a mechanical check.

From Practical: design the robot's motor-driver board in KiCad · PCB Design

I read the fab's capability sheet and enter its numbers in Board Setup, Design Rules, Constraints: minimum clearance, track width, annular width, via and drill sizes and copper to edge. I choose my defaults with margin above those minimums, then define net classes, for example 0.2 mm default, 0.5 mm power and 1.5 mm motor, assigned by net-name patterns. For limits the dialog cannot express I add custom rules in the project's .kicad_dru file, such as a minimum hole size or edge clearance. I also enter the fab's stack-up so thickness and impedance are right, and I rerun DRC after every change.

From Practical: design the robot's motor-driver board in KiCad · PCB Design

For 3 A on a 1 oz outer layer with a 10 °C rise, IPC-2221 gives about 1.4 mm, so VM and the motor outputs use a 1.5 mm net class; the TB6612FNG's pads are narrower, so the traces neck down only at the pads. The 100 µF bulk capacitor goes within 5 mm of the VM pins with a 10 µF and a 100 nF beside it, so the inrush and the PWM edges are supplied locally. The motor return current gets a short, direct path back to the battery connector over a solid ground plane. I check it against the loop-area idea: short, wide and close to the plane.

From Practical: design the robot's motor-driver board in KiCad · PCB Design

The fab gets Gerbers for every copper, mask, silkscreen, paste and outline layer plus the Excellon drill files, normally in one zip. The assembler additionally gets the BOM with supplier part numbers and the position file with reference, X, Y, rotation and side. KiCad exports these from File, Fabrication Outputs, and KiCad 9 can save the whole set as a jobset so it is repeatable. Before ordering I open the Gerbers in a viewer and check the assembler's placement preview for rotation and polarity.

From Practical: design the robot's motor-driver board in KiCad · PCB Design

DRC only checks the board file, so I bring the mechanical constraints into it. I import the chassis DXF onto a user layer, take the outline and hole positions from it, and add keep-out areas for standoff heads, walls and tall neighbours. I place the connectors with that layer visible, review heights in the 3D viewer and export STEP to check against the enclosure model. For a first article I also print the outline at 1:1 and test-fit it before ordering.

From Practical: design the robot's motor-driver board in KiCad · PCB Design

It is the cycle every robot repeats: read the sensors, decide what to do, command the actuators, and start again. On a small ESP32 robot it is literally the body of a fixed-rate loop: read the encoders and line sensors, run the controller and behavior logic, and write PWM duty cycles to the motor driver. It runs at a fixed rate, typically 100 Hz to 1 kHz for wheel control, because the controller math assumes a constant time step. Slower loops sit on top of it, such as a 10-20 Hz behavior state machine or path planner.

From Anatomy of a robot · Robotics

Motors draw large, fast-changing currents: a small gearmotor can pull more than an amp at stall and roughly twice that when it is reversed at full speed. Those spikes, flowing through the battery's internal resistance and the wiring, make the supply sag and ring, and a microcontroller on the same rail can brown out and reset. So the motors run from the raw pack through the driver, and the logic gets its own regulated rail, for example a buck to 5 V and an LDO to 3.3 V, with bulk capacitance at the driver. The grounds still have to be common so signals share a reference, ideally joined at one star point near the battery.

From Anatomy of a robot · Robotics

At 1 m/s and 50 Hz the robot moves 20 mm between decisions, and it can react up to one period late plus actuator delay, so anything narrower than about 20 mm can be missed entirely. I would start from the smallest feature or error I must resolve, say a 19 mm tape line or ±5 mm of position, and pick a rate that keeps travel per cycle well below it, here 200 Hz or more. I would also check it against the dynamics: a loop should run roughly 10-20 times faster than the bandwidth it controls, so a wheel-speed loop with a few hertz of bandwidth is comfortable at 100-200 Hz. Finally I would measure the real period and its worst-case jitter on the hardware, because one blocking call can quietly cut the rate in half.

From Anatomy of a robot · Robotics

A degree of freedom is one independent way something can move. A differential-drive robot on the floor has a 3-DOF pose, x, y and heading, but only two inputs, the wheel speeds, so it cannot move sideways; that is a nonholonomic constraint. To place a tool at any position and orientation in 3D space an arm needs six joints, three for position and three for orientation, like a UR5e. Seven-joint arms such as the Franka or KUKA iiwa add a redundant joint so they can reach around obstacles while holding the same tool pose.

From Anatomy of a robot · Robotics

I give the microcontroller everything with hard timing: PWM generation, encoder counting, the 100 Hz to 1 kHz motor and balance loops, and safety such as current limits and a watchdog. The single-board computer, say a Raspberry Pi or a Jetson, runs the heavy soft-real-time work: camera and lidar processing, mapping and planning at 5-30 Hz, and networking. They talk over UART, USB or SPI, or through micro-ROS on a ROS 2 robot, with the computer sending velocity setpoints and the microcontroller streaming odometry back. The microcontroller must also fail safe on its own: if no command has arrived for about 200 ms it ramps the motors to zero.

From Anatomy of a robot · Robotics

You give the trigger pin a 10 µs pulse, the module sends eight cycles of 40 kHz sound, and it holds its echo pin high until the reflection comes back. Distance is the pulse width times the speed of sound divided by two, about 58 µs per centimetre at 20 °C. It works from about 2 cm to 4 m inside a cone of roughly 15°. It fails on soft materials that absorb sound and on smooth surfaces at an angle, which reflect the sound away like a mirror. The speed of sound also changes by about 0.6 m/s per °C, so a 30 °C swing is roughly a 5% error unless you compensate.

From Sensors · Robotics

It has two outputs, A and B, that produce square waves a quarter cycle apart. If A's edges come before B's the shaft turns one way; if B leads, it turns the other way. Counting every rising and falling edge of both channels, called ×4 decoding, gives four counts per pulse period, so a 7 PPR encoder gives 28 counts per motor revolution. I would count in hardware, such as the ESP32's pulse-counter unit, or in short interrupts that run a 2-bit state machine so reversals and glitches are handled correctly.

From Sensors · Robotics

The gyro measures angular rate with little noise, but integrating it accumulates bias, so the angle drifts; the accelerometer measures the direction of gravity without drift, but it is noisy and fooled by vibration and acceleration. The filter blends them: angle = α·(angle + rate·dt) + (1 − α)·accelAngle, which high-passes the gyro and low-passes the accelerometer. The crossover time constant is about α·dt/(1 − α), so α = 0.98 at 100 Hz gives roughly 0.5 s: the gyro wins for anything faster and the accelerometer for anything slower. It cannot fix yaw, because gravity carries no heading information, so heading needs a magnetometer, a camera or another absolute reference. It also assumes the accelerometer mostly sees gravity, so during long accelerations you lower its weight or move to a Kalman filter.

From Sensors · Robotics

First I look at the noise: spikes and dropouts call for a median of three or five readings, while broadband noise calls for a low-pass such as an exponential moving average. Then I size the filter against the loop, because an EMA with α = dt/(τ + dt) delays slow signals by about τ and that delay eats phase margin. At 100 Hz, α = 0.2 gives τ = 40 ms, which is fine for a 1 Hz heading loop but too slow for a 20 Hz balance loop. If the lag is unacceptable I fix the noise at the source, with better wiring, a better sensor or oversampling, or move to a model-based estimator.

From Sensors · Robotics

Position comes from integrating acceleration twice, so any constant error grows with the square of time. A bias of only 0.01 m/s², about a thousandth of g, becomes ½·a·t² = 18 m of position error after one minute. Tilt makes it worse, because a 1° attitude error leaks 0.17 m/s² of gravity into the horizontal axes. That is why robots use the IMU for orientation and short-term motion, and correct position with wheel odometry, GPS, lidar or cameras.

From Sensors · Robotics

An H-bridge puts four switches around the motor: two high-side switches to the supply and two low-side switches to ground. Turning on one high-side switch and the opposite low-side switch drives current through the motor one way, and the other diagonal pair reverses it. Speed comes from pulse-width modulation at around 20 kHz, so the motor sees duty times supply on average. Brake turns on both low-side switches, shorting the motor so its back-EMF drives a current that opposes rotation and stops it quickly; coast turns everything off and lets it spin down on friction.

From Actuators and motor drivers · Robotics

The L298N uses bipolar Darlington switches that drop about 2 V in total at 1 A, so on a 7.4 V pack the motor sees roughly 5.4 V and the chip burns about 2 W per amp. The TB6612FNG uses MOSFETs with about 0.5 Ω total on-resistance, dropping about 0.5 V at 1 A, so the motor gets more voltage and the board stays cool without a heatsink. It is rated 1.2 A continuous and 3.2 A peak per channel, which suits N20 gearmotors, accepts 3.3 V logic and switches at up to 100 kHz. The L298N only wins when you need its 46 V rating or 2 A continuous.

From Actuators and motor drivers · Robotics

I start from the requirements: mass, wheel radius, top speed, the worst slope and the acceleration I want. The force at the wheels is m·g·sinθ for the slope plus rolling resistance plus m·a, and the torque per motor is that force times the wheel radius divided by the number of driven wheels. Top speed divided by the wheel circumference gives the wheel rpm I need. Then I pick a motor and ratio so the operating point sits at about 20-30% of stall torque, which leaves margin for acceleration and keeps efficiency reasonable, with a no-load speed about 20-30% above my top speed. Finally I check the running current against the driver's continuous rating and the stall current against its peak rating.

From Actuators and motor drivers · Robotics

Shoot-through is both switches in one leg conducting at once, which shorts the supply through two on-resistances; from a stiff battery that can be tens of amps, enough to destroy MOSFETs in microseconds. It happens if the logic commands it, or during transitions, because MOSFETs turn off more slowly than they turn on. Drivers prevent it with interlocks that never allow both inputs of a leg on, and with dead time, a gap of roughly 100 ns to a few microseconds where both switches are off while the inductive current freewheels through the body diodes. Integrated drivers like the TB6612FNG handle this internally; with discrete gate drivers you set the dead time yourself and verify it on a scope.

From Actuators and motor drivers · Robotics

A stepper gives precise open-loop positioning and strong holding torque at low speed, which is why 3D printers use NEMA 17s, but it loses torque as speed rises and silently skips steps if overloaded. A hobby servo is the simplest way to hold an angle within about 180°, such as panning a sensor, because you only send a 1-2 ms pulse every 20 ms. A DC gearmotor with an encoder and a PID loop is best for continuous rotation and efficient driving, as on wheels. On the course robot that means an SG90 for the sensor pan and encoder gearmotors for the wheels.

From Actuators and motor drivers · Robotics

I2C uses two open-drain wires shared by many devices, each with a 7-bit address, at 100 or 400 kHz; it saves pins but is slow and can lock up. SPI uses four wires with a chip-select per device and runs at tens of MHz full duplex, which suits displays, SD cards and fast IMUs. UART is asynchronous point-to-point serial at an agreed baud rate such as 115200, typical for GPS modules, lidars and debug consoles. So I would put the IMU on I2C at 400 kHz unless I need kilohertz sample rates, the display on SPI and the GPS on a UART.

From Microcontrollers and firmware · Robotics

I use interrupts for short, time-critical events that would be missed between polls, such as encoder edges or an echo pin changing, and polling for slow signals that are fine to read once per loop, such as a line sensor or the battery voltage. An ISR should update a volatile counter or timestamp and return within microseconds. It must not call delay(), print to Serial, allocate memory or wait on a bus, because it blocks everything else, including other interrupts. Shared multi-byte variables need an atomic copy in the main code, by briefly disabling interrupts or using a critical section.

From Microcontrollers and firmware · Robotics

I layer it: a hardware abstraction layer (the Arduino core or ESP-IDF drivers), device drivers for the motors, encoders, ultrasonic sensor and IMU, a control layer with PID and odometry, and a behavior layer with a state machine on top. The control step runs on a fixed schedule, either a FreeRTOS task using vTaskDelayUntil with a 10 ms period or a micros()-based loop that adds the period to the deadline so it never drifts. Everything in that step is non-blocking; ultrasonic pings, telemetry and Wi-Fi run at divided rates or in lower-priority tasks. I measure the step's execution time and count overruns, and I add a hardware watchdog plus a command timeout that stops the motors.

From Microcontrollers and firmware · Robotics

First I look at the bus with a scope or logic analyzer: if SDA is stuck low while SCL is high, a slave is holding the line, usually because a reset interrupted a transaction while it was sending a 0. I also check the rise times, because weak pull-ups and long wires cause bit errors that end in the same state. To recover, I reconfigure SCL as a GPIO and clock it up to nine times until the slave finishes its byte and releases SDA, then issue a STOP and re-initialize the driver. Prevention is correctly sized pull-ups, short wiring, a timeout on every transaction, running the bus clear at every boot, and a power switch on the sensor as a last resort.

From Microcontrollers and firmware · Robotics

The Uno's ATmega328P runs at 16 MHz with 2 KB of RAM, 10-bit ADCs and no wireless, which is tight for odometry, PID and telemetry together. The ESP32 has two 240 MHz cores, 520 KB of SRAM, Wi-Fi and Bluetooth, and hardware pulse counters for the encoders, for a few dollars. I would pick an RP2040 when I need deterministic custom I/O from its PIO state machines, and an STM32 when I need advanced motor-control timers and a mature debugging workflow. For a robot that streams telemetry over Wi-Fi, the ESP32 is the natural fit.

From Microcontrollers and firmware · Robotics

P reacts to the present error: the bigger the error, the harder it pushes, but on its own it usually leaves a steady offset because some error is needed to produce any output. I sums the error over time, so it keeps pushing until the offset is gone; too much of it causes overshoot and slow oscillation. D reacts to how fast the error, or better the measurement, is changing, which damps a plant with inertia, but it amplifies noise. On a wheel-speed loop I usually run PI; on heading or position loops, where the plant integrates, D earns its keep.

From Control systems and PID · Robotics

Windup happens when the actuator saturates, say the motor is at 100% duty because the robot is pushing against a wall, and the integral keeps accumulating error it can do nothing about. When the obstacle clears, that huge integral drives a long overshoot. The fixes are to stop integrating while the output is clamped in the same direction as the error (conditional integration), to clamp the integral term itself, or to bleed it back with back-calculation from the saturated output. I also reset or pre-load the integral when the controller is enabled, so the switch-on is bumpless.

From Control systems and PID · Robotics

The error is setpoint minus measurement, so a step change in setpoint makes the error's derivative enormous for one sample, a spike called derivative kick that slams the actuator. The measurement's derivative is the same as the error's except during setpoint changes, so using −dy/dt keeps the damping and removes the kick. I also low-pass filter the D term, typically with a time constant of a few samples, because differentiation multiplies high-frequency noise; at 100 Hz, one encoder count of quantization becomes a large spurious rate. When the sensor measures the rate directly, like a gyro for heading, I use that signal instead of differentiating at all.

From Control systems and PID · Robotics

First I log heading error and the controller's output with timestamps and measure the oscillation period; a steady oscillation means the loop gain at that frequency is too high for the phase lag present. Then I add up the lag: sensor filtering, the loop rate, communication and actuator response. For a heading loop, the oscillation period is roughly four times the total delay, so a 0.7 s period points to about 175 ms of lag. The fixes, in order, are to remove lag (run the loop faster, loosen the filter), add damping with the gyro's rate as the D term, then reduce Kp to about half the value where oscillation began and use a little I for drift.

From Control systems and PID · Robotics

With I and D off, you raise Kp until the output oscillates with constant amplitude; that gain is Ku and the period is Tu. The classic PID table then gives Kp = 0.6·Ku, Ki = 1.2·Ku/Tu and Kd = 0.075·Ku·Tu, or for PI, Kp = 0.45·Ku and Ki = 0.54·Ku/Tu. It aims for quarter-amplitude decay, which means about 25% overshoot, too aggressive for most robots, so I treat it as a starting point and detune. It is also risky on real hardware, because you deliberately drive the system to the edge of instability.

From Control systems and PID · Robotics

In a cascade, an outer loop sets the setpoint of an inner loop: the heading loop outputs a turn-rate command, the turn-rate loop outputs wheel-speed setpoints, and per-wheel PI loops drive the PWM. The inner loops must be 5-10 times faster than the outer ones so the outer loop sees them as nearly ideal, and they reject disturbances such as a carpet edge before the heading even changes. Feedforward adds a model-based guess to the output: duty = kS·sign(v) + kV·v (+ kA·a), from a quick characterization of the motor. With good feedforward the PID only corrects small residuals, so the gains can stay low and the response is fast without overshoot.

From Control systems and PID · Robotics

Linear speed is the average of the wheels, (25 + 15)/2 = 20 cm/s. Turn rate is the difference over the wheel base, (25 − 15)/12 ≈ 0.83 rad/s, counter-clockwise because the right wheel is faster. The instantaneous center of curvature is on the axle line R = v/ω = 24 cm to the left of the robot center. Equal wheel speeds would put R at infinity (straight line) and equal-and-opposite speeds would put it at the center (spin in place). Before sending such a command to motors I would also check saturation and scale both wheels together so the curvature is preserved.

From Kinematics and motion · Robotics

Odometry integrates wheel distances, so every small error is added up and nothing ever corrects it. Systematic errors come from unequal wheel diameters and an uncertain effective wheel base; non-systematic ones from slip, bumps and encoder quantization. Heading error is the dangerous one, because 1° of heading error becomes about 1.7 cm of sideways error for every meter driven afterwards. I would first calibrate the systematic part with a UMBmark square test in both directions, then fuse a gyro for heading, limit acceleration to reduce slip, and add absolute fixes such as markers, a map with lidar, or GNSS outdoors.

From Kinematics and motion · Robotics

The world frame is fixed to the environment; the body frame rides on the robot with x forward and y to the left. Encoders, IMUs and range sensors report in the body frame, while maps, goals and other robots live in the world frame. A rotation by the heading θ converts between them, so a body speed v becomes (v·cos θ, v·sin θ) in the world. The classic bug is adding a sensor point to the map without rotating it by θ, which smears walls into arcs as the robot turns. ROS makes the convention explicit with the map, odom and base_link frames.

From Kinematics and motion · Robotics

With the base at the origin and the target at (x, y), the law of cosines gives cos θ2 = (x² + y² − l1² − l2²)/(2·l1·l2). If that value is outside −1 to 1 the target is out of reach. Otherwise θ2 = ±acos of it gives the elbow-down and elbow-up solutions, and θ1 = atan2(y, x) − atan2(l2·sin θ2, l1 + l2·cos θ2). The workspace is an annulus from |l1 − l2| to l1 + l2; on its edges the two solutions merge at a singularity where det J = l1·l2·sin θ2 = 0, so the arm cannot move radially and joint speeds blow up nearby. In practice I would also enforce joint limits, choose the solution closest to the current pose to avoid flips, and switch to damped least-squares IK for arms with more joints.

From Kinematics and motion · Robotics

I would plan a trapezoidal velocity profile: accelerate at a fixed limit, cruise, then decelerate at the same limit. With a_max = 0.5 m/s² and v_max = 0.3 m/s each ramp takes 0.6 s and 9 cm, the cruise covers the remaining 82 cm, and the move takes about 3.9 s. If the distance were shorter than v_max²/a_max = 18 cm the profile becomes a triangle with peak speed √(a·d). The wheel speed loops track the profile, and an outer loop on the remaining distance trims the final error. If the payload is fragile I would use an S-curve that also limits jerk.

From Kinematics and motion · Robotics

I would mount the two sensors a few millimeters above the floor, straddling the line, and turn their readings into an error: with digital outputs it is −1, 0 or +1, with analog outputs (L − R)/(L + R) gives a proportional error. A PD law, for example turn = 0.6·e + 0.05·de/dt on top of a base speed of 0.5, steers back toward the line, and I would slow the base speed as the error grows so it does not overshoot curves. The important part is the lost-line case: remember which side the line was last seen on and arc or spin toward it, with a timeout of a few seconds before stopping. I would calibrate the threshold on the actual floor and tape, because carpet, glossy tile and sunlight all shift the readings.

From Perception and navigation · Robotics

Hysteresis means using different thresholds to enter and to leave a state. If Avoid starts below 20 cm and ends above 20 cm, an ultrasonic reading that jitters by a centimeter around 20 cm flips the state every tick, and the robot twitches between two actions. With entry at 20 cm and exit at 30 cm, noise smaller than 10 cm cannot cause a transition. You can get a similar effect with a minimum time in state, for example staying in Avoid for at least 0.8 s. Both keep the actuators from chattering and make the behavior predictable enough to test.

From Perception and navigation · Robotics

For a handful of behaviors an FSM is the clearest choice: four states and eight transitions fit on one diagram and are easy to test. As behaviors grow, an FSM's transitions grow roughly with the square of the states, and adding one behavior means editing many transitions. A behavior tree composes behaviors hierarchically with Sequence and Fallback nodes, so adding a recovery is adding a subtree, and priorities are visible as left-to-right order. That is why Nav2 uses BehaviorTree.CPP for navigation with dozens of recovery and planning behaviors. On a microcontroller with three behaviors I would still write a switch statement.

From Perception and navigation · Robotics

Both search a graph such as an occupancy grid. Dijkstra expands nodes in order of cost so far, g, so it explores a growing circle around the start and always finds the shortest path. A* expands in order of f = g + h, where h estimates the remaining cost, so it explores a narrow band toward the goal and often visits ten times fewer cells in open space. If h never overestimates the true remaining cost (admissible), A* is still optimal; Euclidean distance is admissible for any-angle moves and Manhattan distance for 4-connected grids. If h overestimates, A* gets faster but can return a longer path, and with h = 0 it degrades exactly into Dijkstra.

From Perception and navigation · Robotics

To build a map you need to know where you are, and to know where you are you need a map, so SLAM estimates both at once. The robot predicts its motion from odometry, which drifts, and corrects it by matching what the lidar or camera sees against the map built so far. Graph-based SLAM, used by Cartographer and slam_toolbox, stores poses as nodes and measurements as constraints, then solves for the poses that best satisfy all constraints. Loop closure is when the robot recognizes a place it has visited before; that one constraint pulls the whole trajectory back into shape and removes drift accumulated over the loop. The firmware engineer's part matters a lot: good timestamps and clean odometry make SLAM converge.

From Perception and navigation · Robotics

Motors draw large, fast current spikes at start-up and reversal, and their brushes inject noise, so a motor on the same regulated rail as the microcontroller can drag it below its brownout threshold. On this robot the motors run from the pack through the TB6612's VM pin, while a buck makes a clean 5 V rail and the ESP32's LDO makes 3.3 V. The rails must share ground, because every logic level is measured relative to it; without a common ground the driver's PWM input floats. I would also route the motor return current straight back to the pack so it does not flow through the ESP32's ground wire, and put bulk capacitors at the driver.

From Build your smart robot · Robotics

The trigger input works with 3.3 V because its threshold is below that, so TRIG goes straight to a GPIO. The echo output swings to 5 V and ESP32 pins are not 5 V tolerant, so I would put a divider in it: 1 kΩ in series and 2 kΩ to ground gives 5 × 2/3 = 3.33 V. Alternatives are a level-shifter chip or the HC-SR04P variant that runs at 3.3 V. I would also measure the echo with an interrupt rather than a blocking pulseIn, so a missing echo cannot stall the control loop for 38 ms.

From Build your smart robot · Robotics

The N20 motors are rated 6 V but the 2S pack is 8.4 V when full, and the average voltage a motor sees is roughly duty times supply. Capping duty at 6.0 V divided by the measured pack voltage, 71% on a full pack, keeps the motor at its rated voltage, which protects the brushes and the plastic gearbox and keeps top speed consistent as the pack drains. Because the cap is computed from the battery reading every tick, the robot behaves the same at 8.4 V and at 7.0 V. It is a cheap form of supply compensation that also makes the PID gains valid over the whole discharge.

From Build your smart robot · Robotics

I start unpowered: visual inspection, then continuity checks for shorts between each rail and ground. Next I set any adjustable regulator with nothing connected to its output, because many buck modules ship set to 12 V or more. First power comes from a bench supply with a current limit, around 300 mA, and I check every rail and the idle current against my estimate. Then I flash firmware with the motor driver held in standby and bring up one subsystem at a time: serial logs, motors with the wheels off the ground, encoders, each sensor against a known reference. Only after that do I enable closed-loop behaviors, at low speed, with a hand near the power switch, and I log everything so a failure can be replayed.

From Build your smart robot · Robotics

First estimate the rate: 1050 pulses per wheel turn at 100 rpm is 1750 Hz per channel, which an interrupt on the rising edge of channel A handles easily; the ISR reads channel B to get the direction. The ISR must be short and marked IRAM_ATTR, the counters volatile, and the main loop must read and clear them inside a critical section so it never sees a half-updated value. For higher rates, or to count all four edges, I would use the ESP32's PCNT pulse-counter peripheral, which counts in hardware with a glitch filter and no CPU load. And I would keep the encoder wires away from the motor leads, because PWM noise on an encoder line shows up as phantom counts.

From Build your smart robot · Robotics

It is the difference between how a controller behaves in simulation and on hardware, caused by everything the model leaves out or gets wrong. First, actuation: simulated wheels reach the commanded speed instantly and never slip, while real gearmotors have a time constant of tens of milliseconds, a deadband at low duty and slip on smooth floors. Second, sensing: a simulated ultrasonic sensor is a perfect ray, while a real one is a 30° cone with noise, dropouts and specular reflections off angled walls. Third, timing: real sensors update at their own rates and the whole loop has latency, which the simulator usually ignores. I close the gap by modeling the worst of these, randomizing them, and validating on hardware early.

From Simulate before you build · Robotics

Gazebo is the default companion to ROS 2: it loads URDF and SDF models, simulates lidar, cameras and IMUs, and runs the same nodes you deploy, which makes it good for full-stack integration testing. MuJoCo, open-sourced by DeepMind in 2022, has fast and accurate contact dynamics and is the standard for reinforcement learning on legged robots and manipulators. NVIDIA Isaac Sim uses PhysX and RTX ray tracing for photorealistic sensors, so it is used for synthetic training data and large-scale parallel RL with Isaac Lab. For quick education or a single robot, Webots and PyBullet are lighter alternatives.

From Simulate before you build · Robotics

URDF, the Unified Robot Description Format, is an XML file that describes a robot as a tree of links connected by joints. Each link can have visual geometry, collision geometry and inertial properties; each joint has a type (fixed, continuous, revolute or prismatic), a parent and a child link, an origin with xyz and roll-pitch-yaw, and an axis. ROS tools such as robot_state_publisher use it to publish the TF tree, RViz uses it to draw the robot, and Gazebo uses it, often extended with SDF tags, to simulate it. People usually write it with xacro macros so the two wheels are one macro called twice.

From Simulate before you build · Robotics

I would build a latency budget instead of guessing. Say the sensor updates every 60 ms, the filter adds 50 ms, the control period is 10 ms and the motors need 80 ms to respond: that is about 200 ms, during which the robot travels 0.5 × 0.2 = 10 cm. Braking from 0.5 m/s at 2 m/s² takes v²/2a = 6.25 cm. Adding 10 cm of clearance for noise and the robot's own shape gives a threshold of about 26 cm, and I would make it a function of speed so it shrinks when the robot is slow. Then I would verify it in a simulator with that latency modeled and on hardware with a soft obstacle.

From Simulate before you build · Robotics

I identify the parameters that differ between simulation and reality and are uncertain: friction, motor gain and time constant, mass, sensor noise, latency, dropout rate, sensor mounting angle and start pose. For each I pick a range that brackets the real value, for example 50 to 200 ms of latency, and draw new values every episode, so the controller has to work across the whole range rather than at one point. The ranges should come from measurements on the real robot where possible, because ranges that are too wide make the task impossible and ranges that are too narrow miss the real world. I then measure success as a distribution over hundreds of randomized runs and only move to hardware when the worst decile is acceptable.

From Simulate before you build · Robotics

A topic is a typed, many-to-many stream for continuous data: a lidar publishes sensor_msgs/msg/LaserScan on /scan at 10 Hz and any node can subscribe. A service is a request-response call for short operations, such as enabling the motors or resetting odometry, where the caller waits for an answer. An action is for long-running goals that need feedback and cancellation, like Nav2's NavigateToPose: you send a goal, receive the distance remaining as feedback, and can cancel it if a person steps in front. Under the hood actions are built from topics and services. Choosing wrong hurts: a 30-second navigation done as a service blocks the caller and cannot be cancelled cleanly.

From ROS 2 and the robotics stack · Robotics

TF keeps a time-stamped tree of coordinate frames so any node can ask where one frame was relative to another at a given time, with interpolation. By REP 105, base_link is fixed to the robot, odom is a world frame in which the robot's pose is smooth and continuous but drifts, and map is a world frame that is globally correct but can jump when localization corrects itself. Wheel odometry or an EKF publishes odom to base_link; AMCL or SLAM publishes map to odom, which absorbs the drift without making the odometry discontinuous. robot_state_publisher publishes the fixed sensor frames from the URDF. Local control uses odom because it never jumps; global planning uses map.

From ROS 2 and the robotics stack · Robotics

I would lead with a 60 to 90 second video of the robot doing its job, then walk through a block diagram and the decisions behind it, such as why the TB6612 and why a separate 5 V rail. The strongest part is measured numbers and failures: the brownout I found with a scope and fixed with a bigger buck and bulk capacitance, and how a UMBmark square test cut odometry error from 41 cm to 6 cm. I would show that I tested in simulation first and what changed on hardware. Interviewers care less about the robot's features than about how I debugged, measured and documented it.

From ROS 2 and the robotics stack · Robotics

First I confirm what DDS sees: ros2 topic info -v on the topic lists every publisher and subscription with its QoS, so I check that both endpoints appear and that reliability, durability and deadline are compatible; a RELIABLE subscriber never matches a BEST_EFFORT publisher. If the subscription is missing, I check names and namespaces, remappings and the exact message type. If the publisher is invisible, I check ROS_DOMAIN_ID, the RMW implementation on each machine, and whether multicast discovery is blocked by the network or a firewall, which is common on Wi-Fi and in Docker. Finally I look for an executor problem: a callback group that is never spun, or a single-threaded executor blocked by a long callback.

From ROS 2 and the robotics stack · Robotics

I would run micro-ROS on the ESP32: an XRCE-DDS client publishes /odom and range data and subscribes to /cmd_vel, and a micro-ROS agent on the laptop bridges it over serial or Wi-Fi UDP into the normal DDS graph. Hard real-time work, the 100 Hz wheel speed loops and encoder interrupts, stays on the microcontroller, and only setpoints and state cross the link, at 20 to 50 Hz. I would timestamp messages after syncing the clock with the agent, use best effort for high-rate sensor data and reliable for commands, and add a /cmd_vel watchdog that stops the motors if no command arrives for 300 ms. On a larger robot I would instead write a ros2_control hardware interface so the standard diff_drive_controller does the kinematics.

From ROS 2 and the robotics stack · Robotics

The cells connect through a main fuse, often a pyrotechnic fuse the airbag controller can fire, and two main contactors to the HV bus. A precharge contactor and resistor first charge the inverter's DC-link capacitors so the main contactor closes without an inrush. The inverter turns the DC bus into three-phase AC with six switches and, by controlling motor current, controls torque. The motor drives a single-speed reducer of about 9:1, then the differential and half-shafts. The DC-DC converter, on-board charger, DC fast-charge contactors and the electric compressor and heaters hang off the same bus, and the vehicle controller turns pedal position into a torque request within the limits the BMS and inverter publish.

From EV powertrain architecture · EV Powertrain

An electric motor makes full torque from zero speed and stays efficient up to 16,000-20,000 rpm, so it does not need gears to stay in a narrow power band the way an engine does. One ratio of about 9:1 gives strong launch torque and still reaches top speed within the motor's speed limit. Dropping the gearbox removes a clutch, shift actuators, mass and losses, and a fixed gear stage runs at about 97-98% efficiency. Two-speed units exist, such as the rear unit of the Porsche Taycan, but they target top speed and launch, not everyday efficiency.

From EV powertrain architecture · EV Powertrain

For the same power, doubling the voltage halves the current: 150 kW is 375 A at 400 V but 187.5 A at 800 V, so I²R loss in cables, connectors and contactors falls by a factor of four, or you can halve the copper for the same loss. The headline benefit is charging, because DC chargers and cables top out around 500 A, which caps a 400 V car near 200 kW while an 800 V car can use a full 350 kW unit. The cost is that every HV part must handle peaks near 1,000 V: inverter switches move from 650 V to 1,200 V devices, which is efficient mainly with SiC MOSFETs, and connectors, insulation and creepage distances grow. You also need a way to charge at older 400 V stations, either a separate DC-DC booster or reusing the motor and inverter as a boost converter, as Hyundai's E-GMP platform does. So 800 V pays off in large, fast-charging, high-power cars, while 400 V stays cheaper for compact ones.

From EV powertrain architecture · EV Powertrain

The battery comes first: the BMS charge-power limit collapses when cells are cold, because of lithium plating risk, and when they are nearly full, because there is no voltage headroom. Then come motor and inverter current limits, the fade of regen at very low speed where back-EMF vanishes, and stability, since regen only acts on the driven axle and too much on a rear-drive car on ice can lock the rear wheels. The brake controller asks how much regen torque is available right now, uses it first, and fills the rest of the driver's demand with hydraulic pressure, which is why EVs use brake-by-wire or a decoupled pedal. A good blend keeps total deceleration constant even when available regen changes in the middle of a stop.

From EV powertrain architecture · EV Powertrain

The inverter's DC-link capacitor bank, a few hundred microfarads to about a millifarad, looks like a short circuit when it is empty. Closing the main contactor straight onto a 400 V pack would drive an inrush of thousands of amps limited only by milliohms, which welds contacts and stresses the capacitors. Instead the BMS closes the negative contactor and a precharge contactor in series with a resistor, waits a few hundred milliseconds until the bus reaches about 95% of pack voltage, then closes the main positive contactor and opens the precharge path. If the bus voltage does not rise on schedule, that also flags a short or leak on the HV bus before full power is applied.

From EV powertrain architecture · EV Powertrain

Three windings sit 120° apart around the stator, and the inverter drives them with currents 120° apart in time. Each winding makes a field that only pulses along its own axis, but when you add the three vectors the pulsing parts cancel and the sum has a constant length, 1.5 times one phase's peak, pointing in a direction that turns at the electrical frequency. With more poles the pattern repeats around the stator, so it turns mechanically at 120·f/p rpm. Swapping any two phases reverses the rotation, which is all reverse gear is in an EV.

From Three-phase motors · EV Powertrain

Slip is the fraction by which the rotor turns slower than the field, s = (n_s − n)/n_s. An induction rotor has no magnets; its bars only carry current while the field sweeps past them, so at exactly synchronous speed there would be no induced current and no torque. At rated load slip is typically 1-5%, and in that range torque rises roughly in proportion to slip. The rotor currents run at the slip frequency s·f, and the rotor copper loss equals slip times the air-gap power, which is why induction rotors run hot and are hard to cool.

From Three-phase motors · EV Powertrain

The 2008 Roadster and the original Model S and X used induction motors: no rare earths, rugged, and no back-EMF or drag when unpowered. But an induction motor needs magnetizing current and has rotor copper loss, so it is less efficient at the light loads where cars spend most of their time. The Model 3 (2017) introduced an interior-PM synchronous reluctance motor, where magnets buried in the rotor's flux barriers add magnet torque to reluctance torque, which raises efficiency across the drive cycle. In a dual-motor Model 3 the front motor stays induction, because when it is not needed it can be switched off completely and spins with no magnet losses. The PM motor does the efficient everyday work, and the induction motor adds peak power at almost no cost when idle.

From Three-phase motors · EV Powertrain

Back-EMF in a PM motor rises in proportion to speed, and above base speed it would exceed the voltage the inverter can make from the DC bus, so current and torque would collapse. Field weakening injects negative d-axis current whose flux opposes the magnets, lowering the net flux linkage so the motor can keep accelerating at roughly constant power. The first risk is to the magnets: that reverse field adds to the demagnetizing stress, and hot NdFeB has less coercivity, so it can be pushed past the knee and lose flux permanently. The second is a fault at high speed: if the inverter stops switching, the full back-EMF can exceed the bus voltage and drive uncontrolled current through the diodes into the pack, so drives use an active short circuit, all three low-side switches on, as the safe state.

From Three-phase motors · EV Powertrain

Hairpins are rectangular copper bars bent into a U, pushed axially into the slots and laser-welded at the other end. Rectangular conductors pack far better than round wire, about 70% slot fill against roughly 45%, so DC resistance and copper loss fall and heat flows more easily into the lamination stack. They also suit automated insertion and welding, which is faster and more repeatable than winding round wire. The catch is AC loss: at high frequency, current crowds into part of a thick bar through skin and proximity effects, so designers use more, thinner layers, typically four to eight per slot.

From Three-phase motors · EV Powertrain

Each phase has a half-bridge, two switches in series across the DC link, so the phase output can only be tied to the positive or the negative rail. PWM switches it between them thousands of times a second, typically 8-20 kHz, and varies the fraction of time spent high so the average over each switching period follows a sine. In sine-triangle PWM the controller compares a sinusoidal reference with a triangular carrier, and the leg is high whenever the reference is above the carrier. The motor's inductance filters the pulses, so the current is a smooth sine with a small ripple at the switching frequency.

From Inverters, PWM and field-oriented control · EV Powertrain

Dead time is a short gap, about 0.1-0.5 µs for SiC and 1-2 µs for IGBTs, when both switches of a leg are off, so one switch is fully off before the other turns on and the DC link is never shorted. During the gap the load current keeps flowing through a diode, so the output voltage is set by the current direction instead of the command. The average error is td × fsw × Vdc: 1 µs at 10 kHz on a 400 V bus is 1%, or 4 V. Because the error flips sign with the current, it distorts the current near every zero crossing and matters most at low speed, where the commanded voltage is small, so controllers compensate for it.

From Inverters, PWM and field-oriented control · EV Powertrain

Two or three phase currents are sampled in the middle of the PWM period, and the Clarke transform turns them into two stationary components, α and β. The Park transform rotates those by the rotor's electrical angle, from a resolver or an observer, into the d-q frame, where steady sinusoids become DC values: Id along the magnet flux and Iq at 90° to it, which makes torque. Two PI controllers drive Id and Iq to their references, with Iq from the torque request and Id from zero, an MTPA table or field weakening, and their outputs are d-q voltage commands. The inverse Park transform rotates those voltages back to α-β, space-vector PWM turns the vector into three duty cycles using the measured DC-link voltage, and the gate drivers switch the six devices. The loop runs at the PWM rate, 10-20 kHz, with a current bandwidth around 1 kHz.

From Inverters, PWM and field-oriented control · EV Powertrain

SiC MOSFETs are majority-carrier devices with no IGBT tail current and very little reverse-recovery charge, so their energy per switching event is several times lower. That lets them run at 20 kHz or more with less loss than a silicon IGBT at 10 kHz, giving a quieter, smoother current or simply higher efficiency at the same frequency. The cost is edge speed: 20-50 V/ns stresses the motor's winding insulation, drives common-mode current through the bearings and makes EMI harder to contain. Gate drivers need common-mode transient immunity above 100 kV/µs, a tight low-inductance layout and fast short-circuit protection, because a SiC die survives a short for only about 2-3 µs against roughly 10 µs for an IGBT.

From Inverters, PWM and field-oriented control · EV Powertrain

Hardware overcurrent comparators on the phase currents shut the gates within microseconds, without waiting for software. Desaturation detection in each gate driver catches shoot-through and short circuits by watching the switch's on-state voltage, then turns it off softly to limit overshoot. DC-link overvoltage protection covers regen when the contactors open, and module thermistors plus a junction-temperature model derate current before the devices overheat. For PM motors the drive also needs a safe state at high speed, usually an active short circuit with all three low-side switches on, so back-EMF cannot pump uncontrolled current into the bus.

From Inverters, PWM and field-oriented control · EV Powertrain

Series groups add voltage and parallel cells add capacity, so pack voltage is s times the cell voltage, capacity is p times the cell amp-hours, and energy is their product. For 96s46p with 4.8 Ah, 3.6 V cells that is 345.6 V, 220.8 Ah and about 76.3 kWh. Full charge is 96 × 4.2 = 403 V and empty is about 96 × 3.0 = 288 V, so the inverter and charger must work across that whole window. The same 4,416 cells wired 192s23p give the same energy at twice the voltage and half the current, which is the 800 V trade.

From Batteries and the BMS · EV Powertrain

It measures every series group's voltage to a few millivolts, temperatures across the pack and the pack current. From those it estimates state of charge and state of health and continuously publishes charge and discharge power limits to the inverter and charger. It balances the groups, sequences the precharge and main contactors, monitors insulation resistance between the high-voltage bus and the chassis, and opens the contactors on overvoltage, undervoltage, overcurrent, overtemperature, an isolation fault or a crash signal. It also asks the thermal system to heat or cool the pack.

From Batteries and the BMS · EV Powertrain

Charging is constant current until a cell reaches its voltage ceiling, about 4.2 V for nickel-rich cells, then constant voltage while the current decays, so the last 10-20 % is always slow. Well before that, the BMS lowers current as state of charge rises because the graphite anode is filling and its potential approaches that of lithium metal; pushed harder, lithium plates on the surface instead of inserting, which permanently costs capacity and can grow dendrites. Cold makes this much worse because resistance and diffusion times rise steeply, so a cold pack may be held to a fraction of its warm power. Preconditioning heats the pack on the way to the charger so the BMS allows high current from the moment you plug in. That is why the useful fast-charging window is roughly 10-80 %.

From Batteries and the BMS · EV Powertrain

Coulomb counting integrates current but drifts with sensor offset and gain error, so it needs periodic correction from the open-circuit voltage after the pack rests. NMC's open-circuit voltage changes steadily with state of charge, but LFP sits on a plateau near 3.3 V across most of its range, so a few millivolts of error can mean many percent of state of charge. LFP systems therefore lean on the steep ends of the curve: a regular charge to 100 % recalibrates the estimate, which is why some makers recommend frequent full charges for LFP. Model-based estimators such as Kalman filters, with temperature and hysteresis models, carry the estimate in between.

From Batteries and the BMS · EV Powertrain

Passive balancing switches a resistor across the highest groups and burns their excess charge as heat until they match the lowest, typically at tens to a couple of hundred milliamps. It is cheap and simple but only removes charge, so it cannot recover capacity from a weak group. Active balancing moves charge from high groups to low ones with inductors, capacitors or small DC-DC converters, which saves energy but costs parts, board area and complexity. Most EV packs use passive balancing because well-matched cells only need small, occasional corrections.

From Batteries and the BMS · EV Powertrain

Start at the cell: a vent and current-interrupt device in the cap, and per-cell fusing such as the thin wire bonds Tesla uses, which open if one cell shorts. Then slow heat transfer between cells with spacing, mica or aerogel barriers and coolant, and give hot gas a defined vent path out of the pack and away from the cabin. The BMS watches for early signs such as a sudden voltage drop or temperature rise, opens the contactors and warns the occupants. Chemistry is the last lever: LFP releases far less oxygen and heat than NCA or NMC, which is one reason it is chosen for standard-range and stationary packs.

From Batteries and the BMS · EV Powertrain

An induction motor has no magnets: the rotor is laminated steel with conducting bars shorted by end rings, and the stator field induces the rotor current through slip. That avoided rare-earth cost and supply risk and any demagnetization limit, and the rotor is very robust at high speed. With the inverter off there is no rotor field, so a fault at speed cannot generate uncontrolled voltage and the motor freewheels with little drag. Tesla made it efficient enough with copper rotor bars, liquid cooling and careful inverter control.

From Tesla Roadster and motor evolution · EV Powertrain

It is an interior permanent magnet motor whose rotor also has flux barriers, so it makes magnet torque plus reluctance torque from the steel trying to align with the stator field. The magnets supply the rotor field without any magnetizing current, so efficiency is high at light load, which is where a car spends most of its highway driving. The reluctance contribution lets designers use less magnet and gives a wide field-weakening range for power at high speed. The costs are magnet supply risk, a demagnetization limit at high temperature, and drag from the magnets when the motor spins unpowered.

From Tesla Roadster and motor evolution · EV Powertrain

Power is torque times speed, and torque is set by rotor size and current, so spinning faster is the cheapest way to get more power from the same size of machine. Centrifugal hoop stress grows with the square of speed; at about 20,000 rpm the surface of a rotor 140 mm across moves at roughly 147 m/s, enough to tear magnets and thin steel bridges loose. A carbon-fiber sleeve wound under tension pre-loads the rotor so it stays together, and because it is non-magnetic and far less conductive than metal it adds little eddy-current loss. The trade-offs are heat, since the sleeve insulates the rotor while the magnets must stay below their demagnetization temperature, and a slightly larger magnetic gap.

From Tesla Roadster and motor evolution · EV Powertrain

First label them correctly: they are claims from the November 2017 announcement, the car was promised for 2020 and has been delayed repeatedly, so I would check Tesla's site for its current status before quoting them. Then test them with physics. 0-60 mph in 1.9 s means reaching 26.8 m/s in 1.9 s, an average of about 14 m/s² or 1.44 g, at or beyond the grip limit of road tires. A 200 kWh pack at 160-200 Wh/kg would weigh 1,000-1,250 kg, and 620 miles from 200 kWh implies about 320 Wh per mile, plausible for a fast, heavy car. So the range claim is physically consistent, while the acceleration claim depends on tires, the launch surface and the proposed thrusters.

From Tesla Roadster and motor evolution · EV Powertrain

A motor's back-EMF rises with speed, and once it reaches what the inverter can produce from the DC bus, no more current can be pushed in to make torque. The controller then drives current that opposes the rotor field: negative d-axis current in a permanent-magnet machine, or less magnetizing current in an induction machine, which keeps the back-EMF within the bus voltage. Torque then falls roughly as 1/speed, so power stays roughly constant until losses, current limits or breakdown torque take over. That wide constant-power band is why a single fixed gear can cover a car's whole speed range.

From Tesla Roadster and motor evolution · EV Powertrain

Batteries charge on DC, so the question is where the conversion happens. With AC charging the wall box only switches and protects, and the car's on-board charger rectifies the AC, so power is limited to roughly 7-19 kW by what is practical to carry in the car. With DC fast charging the station rectifies and converts, delivering 50-350 kW straight to the battery through the car's DC contactors, while the car's BMS tells the charger how much current to supply. That is why DC chargers are large, expensive, liquid-cooled cabinets and AC chargers are relatively simple boxes.

From EV charging systems · EV Powertrain

They cover different links. ISO 15118, like the older DIN SPEC 70121, runs between the car and the charger as powerline communication on the pilot wire: limits, the current-demand loop, Plug & Charge certificates and, in ISO 15118-20, bidirectional power. OCPP runs between the charger and the operator's backend over a WebSocket: authorization, transaction start and stop, meter values for billing, status, firmware updates and smart-charging profiles that cap power. A good mental model is that ISO 15118 decides how this car charges, and OCPP lets an operator run and bill a whole fleet of chargers.

From EV charging systems · EV Powertrain

Nameplate is 1.2 MW, but with 2:1 sharing the cabinets deliver at most 600 kW, so I size from the managed cap, which NEC 625.42 allows when an automatic load management system enforces it. At 95 % efficiency and 0.99 power factor that is about 638 kVA, plus about 15 kVA of lighting and controls, roughly 653 kVA, so a 750 kVA transformer. At 480 V that is about 785 A, and 125 % for a continuous load gives about 982 A, so a 1,000 A main. I would also ask about the utility's demand charges, leave conduit and pad space for growth, and lay out the accessible stalls and cable reach before the electrical design is frozen.

From EV charging systems · EV Powertrain

Everything in the power path is thermally limited: the power modules' semiconductors, the magnetics, and especially the cable and connector, whose heating goes as current squared. A liquid-cooled cable dumps its heat through a small radiator, so high ambient, direct sun or a clogged radiator raises the coolant temperature until the connector's pin sensors force a lower current. You can spot a cable limit because cars with different pack voltages derate to the same current rather than the same power. At the site level I would add shade and clear airflow, put radiator cleaning on the maintenance plan, alarm on OCPP cable-temperature and derate events, and specify equipment by its derating curve at the local design ambient.

From EV charging systems · EV Powertrain

Through the control pilot, a 1 kHz, ±12 V square wave generated by the EVSE. The duty cycle sets the limit: between 10 % and 85 % duty, amps = duty × 0.6, so 50 % means 30 A, and 85-96 % covers 51-80 A. The car signals its state by loading the pilot with resistors, 9 V for connected and 6 V for ready, and the EVSE only closes its relay once it sees 6 V. A 5 % duty cycle is special: it means digital communication is required, which is how DC fast charging sessions begin.

From EV charging systems · EV Powertrain

It is Tesla's connector, opened as the North American Charging Standard in November 2022 and standardized by SAE as J3400. It is small, carries AC and DC on the same pins, and came with the largest fast-charging network in North America, so automakers gained access to that network by adopting it. Most announced a switch for new models, with adapters bridging CCS1 cars in the meantime. For site designers it means planning for both connectors for years, often on the same dispenser.

From EV charging systems · EV Powertrain

A mesh approximates a surface with triangles, so a cylinder is a ring of flat facets and nothing in the file says it was ever a cylinder. A B-rep stores faces, edges and vertices with exact surfaces and curves, plus the topology of which entities touch, so the same cylinder is one face with a radius. That is why a machine shop wants STEP, which carries a B-rep, rather than STL, which carries a mesh. Meshes are still the right choice for rendering, 3D printing and machine-learning datasets because they are simple and robust.

From CAD kernels and parametric design · AI-Assisted Design

Parasolid from Siemens sits under SolidWorks, NX, Solid Edge and Onshape. ACIS from Spatial is licensed to many vendors, and Autodesk's ShapeManager in Inventor and Fusion started as a fork of it. OpenCascade is the open-source kernel behind FreeCAD, CadQuery and build123d, and KiCad uses it for STEP import and export. CATIA has its own CGM kernel and Creo has Granite. The kernel matters because boolean and fillet robustness differ between them, so a model can rebuild in one tool and fail in another.

From CAD kernels and parametric design · AI-Assisted Design

A feature tree is the ordered recipe of a history-based CAD model: sketch, extrude, hole, fillet, pattern. On every edit the kernel replays the recipe from the top, and each feature takes the previous result as its input. Order matters because later features reference geometry that earlier ones create. A fillet placed after a hole has to roll around that hole, so enlarging the hole can break it, while the same fillet built first never sees the hole. As a rule I build large global features first, add holes and small details last, and select geometry by rule instead of by name.

From CAD kernels and parametric design · AI-Assisted Design

STEP carries exact B-rep geometry with units, assembly structure and optionally colours or GD&T, so it is the hand-off to a machine shop or another CAD tool. STL carries only triangles with no units or colour, which is fine for a slicer but loses every dimension. 3MF is a zipped XML package that holds a mesh with units, colours, materials and multiple objects, so it is the modern choice for 3D printing. I choose by who consumes the file: a machinist gets STEP, a printer gets 3MF or STL, and a renderer gets glTF or OBJ.

From CAD kernels and parametric design · AI-Assisted Design

Features in a history-based model refer to faces and edges by identifiers the kernel generates, such as Edge17. After an upstream edit the kernel may split, merge or renumber entities, so a downstream fillet can attach to a different edge or fail outright. Commercial systems keep persistent IDs with heuristics, and FreeCAD added element tracking in version 1.0 to mitigate it. In design terms I reduce exposure by referencing sketch geometry or datum planes instead of picked faces, by ordering features so fragile references come late, and in code-CAD by selecting with queries such as edges parallel to Z at the corners. I also add a check that fails loudly when a selection returns zero or an unexpected number of entities.

From CAD kernels and parametric design · AI-Assisted Design

Code-CAD turns geometry into text, which is the medium a language model is best at: the model writes build123d or CadQuery, the script runs headless, and any error comes back as a traceback it can read and fix. The result is diffable, so a review shows that a hole changed from 6.5 to 8.5 mm instead of showing a binary file that changed. Parameters are explicit, so a checker can inspect them and a tool can reject values outside the shop's limits. The limits are spatial and physical: the model cannot see the part unless you give it renders or measurements, it mixes up axes and mirrored features, and it knows nothing about tolerances or the shop's tooling unless a check encodes them. So I pair code-CAD with measurement tools and DFM checks rather than trusting the script.

From CAD kernels and parametric design · AI-Assisted Design

I start with requirements that carry units and test conditions, then generate the systems level: a P&ID for the refrigerant loop and a single-line and wiring diagram, both as graphs. Next come real components matched to each duty, and an end-to-end simulation that returns heat output, COP and current. Only then does the agent write geometry through a CAD kernel, followed by DFM and DFA checks that return diagnostics, and finally subassemblies and an assembly order. Each stage has a machine check, and failures loop back to the cheapest stage that can fix them, so an undersized compressor returns to component selection instead of surviving into 3D.

From AI agents for hardware design · AI-Assisted Design

DFM asks whether a single part can be manufactured: bend radius, wall thickness, hole-to-edge distance and flange length against the shop's capabilities. DFA asks whether parts can be assembled: a free insertion path, tool access to every fastener, a valid order and few reorientations. They fail independently, which is why a bracket can pass every DFM rule and still be impossible to install behind a coil. I want both as compile-time checks, because anything the pipeline does not check it silently assumes.

From AI agents for hardware design · AI-Assisted Design

It is good at search across large catalogs, at boilerplate such as BOMs, wire lists and parametric variants, and at keeping names, units and identifiers consistent across schematic, BOM and 3D. It is weak at tolerances and fits, at tacit shop knowledge such as what a press brake can hold, at physics nobody simulated, and at mirrored or left-right geometry. It also invents plausible part numbers and datasheet values. So I use it where results can be checked mechanically and keep a human on the decisions that depend on judgement.

From AI agents for hardware design · AI-Assisted Design

The stages are the same with different artifacts. Requirements are stalls, kW per stall and the utility service, which become a single-line diagram and a load calculation. Components are the transformer, switchboard, conductors and chargers, and the simulation checks voltage drop and load management. Geometry is the stall layout and trench routes, and the code checkers (NEC 625 and accessibility rules) play the role of DFM. The loops are also the same: an overloaded service returns to component selection, and a failed clearance returns to the layout.

From AI agents for hardware design · AI-Assisted Design

I would score it against a fixed rubric in three layers. Rule checks cover traceability, schematic completeness, real parts, layout versus schematic, DFM and DFA. Simulation covers the energy balance, performance against the spec, a COP that sits at a plausible fraction of Carnot, and electrical sizing against the minimum circuit ampacity. Human review covers what was never modelled, such as vibration, defrost and refrigerant charge limits, a prototype test plan and a named engineer who signs. I also require reproducible source, because every change should be a reviewable diff. Anything unknown counts as a fail until it is checked.

From AI agents for hardware design · AI-Assisted Design

A compile-time check gives fast, deterministic feedback with exact numbers, such as a hole rim 4.9 mm from the edge against 6.5 mm required. An agent can read that, fix the geometry and rerun in seconds, which is the loop that makes generation converge instead of guess. Errors found early are cheap, since a wrong line size costs seconds in a simulator and a recall in the field. The limit is that a checker only knows the rules someone wrote, so a green report proves those rules and nothing more. I treat it as one verification layer next to simulation and human review.

From AI agents for hardware design · AI-Assisted Design

MCP is an open protocol from Anthropic, announced in November 2024, for connecting AI applications to tools and data in a standard way. Before it, every application needed a custom integration for every tool. With MCP a server exposes tools, resources and prompts over JSON-RPC 2.0, and any compliant host can discover and use them. The host runs a client per server, and the model sees each tool as a name, a description and an argument schema.

From Build a Claude CAD tool with MCP · AI-Assisted Design

You list the server under mcpServers in claude_desktop_config.json with a command and arguments. Claude Desktop starts that command as a subprocess and exchanges newline-delimited JSON-RPC messages over its standard input and output, which is the stdio transport. The client calls initialize, then tools/list, and later tools/call whenever the model wants to run a tool. Because stdout is the protocol channel, the server must never print to it, and logs go to stderr.

From Build a Claude CAD tool with MCP · AI-Assisted Design

The description says what the tool does, what units it uses and what it will refuse, because the model reads it to decide when and how to call the tool. The schema carries the types and the hard limits, such as thickness at least 1.5 mm, so the model sees them before calling and the server can reject violations before any code runs. Together they act as part of the prompt that cannot be argued with. I write them as carefully as the code, and I include an example of a good call when the arguments are not obvious.

From Build a Claude CAD tool with MCP · AI-Assisted Design

The model can run unintended or destructive code, and its arguments can be influenced by untrusted text in documents or web pages. The server runs with your permissions, so the first containment is not to expose a general run_python tool at all and to offer small typed tools instead. If code execution is unavoidable, I run it in a container or a restricted subprocess with a timeout, a memory limit, no network and one writable folder. I also keep per-call approval on during development and review transcripts for what actually ran.

From Build a Claude CAD tool with MCP · AI-Assisted Design

I would use layers. Typed tools with schema limits and validation reject impossible input with errors that say what to change. A checker such as dfm_check measures the real geometry, and export is gated on it so verification cannot be skipped. The server writes to one folder, restricts names, and caps sizes and run time so a bad request cannot damage the machine or hang it. I would test it with unit tests, the MCP Inspector and a corpus of known-bad designs that must fail, because a checker that has never failed proves nothing. Finally I would keep a human review and a physical prototype for anything that goes to manufacturing.

From Build a Claude CAD tool with MCP · AI-Assisted Design

I stop treating it as a prompting problem, because a prompt competes with the user's request and the model will trade the rule away. I move the constraint into the tool: a schema limit so the model sees it up front, validation that returns an actionable error, and a checker that measures the actual geometry. Then I gate the irreversible step, such as export, on that checker passing. I add a regression test with a design that violates the rule, which must fail the check and must not export. After that the model can still try, but it can no longer succeed, and the error text teaches it the limit.

From Build a Claude CAD tool with MCP · AI-Assisted Design