Semiconductors

The industry map and the jobs

EDA, fabless, foundry, IDM, equipment and OSAT, and which roles a two-week learner can target.

Day 3 · 40 min

After this lesson

You can describe the semiconductor value chain with the major companies at each step.
You can explain what process, device, design, applications and test engineers do.
You can structure a failure-analysis answer in an interview.

Who does what, and where you fit

A chip passes through several specialist industries before it reaches a phone or a car. Knowing who does what tells you where the jobs are, what each company buys and sells, and what its interviews will ask.

The value chain

EDA. Synopsys, Cadence and Siemens EDA (formerly Mentor Graphics) sell the software used to simulate, synthesize, place, route and verify chips. Synopsys bought Ansys for about $35 billion in 2025.
IP. Arm licenses CPU cores and its instruction set, and more than 250 billion Arm-based chips have shipped. Synopsys and Cadence also sell interface IP such as USB, PCIe and DDR; RISC-V offers an open alternative.
Fabless. NVIDIA, Qualcomm, AMD, Apple, Broadcom and MediaTek design chips and own the customer but have no fabs. AMD went fabless in 2009 when it spun its fabs out as GlobalFoundries.
Foundry. TSMC holds about two-thirds of foundry revenue and nearly all leading-edge logic. Samsung shipped the first gate-all-around 3 nm process in 2022, Intel Foundry now builds for outside customers, and GlobalFoundries focuses on mature and specialty nodes.
IDM. Intel, Texas Instruments, Infineon, STMicroelectronics, NXP and Micron design and manufacture their own products. Analog and power companies stay IDMs because their process is their product.
Equipment. ASML (lithography, the only EUV maker), Applied Materials (deposition, etch, implant, CMP), Lam Research (etch and deposition), Tokyo Electron (coater/developer tracks, etch) and KLA (inspection and metrology). Shin-Etsu and SUMCO supply most wafers.
OSAT. ASE, Amkor and JCET package and test chips; TSMC and Intel also do advanced packaging in-house.

What moves between stages (GDSII, wafers, good dies, packaged chips), how long each stage takes, and which business model covers it. An IDM keeps design, fabrication and often assembly under one roof.

Moore’s law, briefly

In 1965 Gordon Moore noted that components per chip were doubling every year; in 1975 he revised it to every two years. The trend held for five decades: Intel’s 4004 of 1971 had 2,300 transistors on a 10 µm process, Apple’s M1 in 2020 had 16 billion, and NVIDIA’s B200 in 2024 has 208 billion across two dies. Dennard scaling, which kept power density constant as transistors shrank, broke down around 2005, so clock speeds stalled near 3-5 GHz. Gains moved to more cores, accelerators, new transistor shapes (FinFET, first shipped by Intel in 2012; gate-all-around from 2022) and advanced packaging. Node names such as “3 nm” are now labels: nothing on the chip is 3 nm wide.

Policy: the CHIPS Act and export controls

Leading-edge production is concentrated in Taiwan and South Korea, so governments now treat chips as strategic. The US CHIPS and Science Act of August 2022 provides $52.7 billion, including $39 billion of manufacturing incentives, plus a 25% investment tax credit for new fabs (raised to 35% in 2025); it funded projects by TSMC, Intel, Samsung and Micron. Since October 2022, US export controls restrict advanced AI chips and chipmaking tools to China, and the Netherlands and Japan restrict EUV and advanced DUV tools; ASML has never shipped an EUV scanner to China. New fabs and packaging plants in Arizona, Texas, Ohio and New York will need engineers and technicians for years.

The roles and what interviews ask

Role	What you do	What interviews probe
Process engineer	Own one unit process (etch, litho, CMP) in a fab: recipes, SPC, excursions	Process physics, control charts, design of experiments, a yield story
Device engineer	Design and characterize transistors; build models for designers	MOSFET physics, I-V curves, leakage, reliability (BTI, HCI, TDDB)
Design engineer	Digital RTL and timing, or analog blocks such as regulators and ADCs	Verilog, setup and hold, CMOS circuits, op-amps and feedback
Verification engineer	Prove the design works before tape-out with testbenches and coverage	SystemVerilog, UVM, assertions, debugging a failing test
Applications / field applications	Help customers design the chip in: reference designs, board debug, app notes	Datasheets, board-level debug, power conversion, a customer role-play
Product / test engineer	Write ATE test programs, characterize parts over temperature, cut test time	Test coverage, DPPM, guardbands, bin analysis, Python
Yield engineer	Find and kill defect sources with wafer maps, inspection data and statistics	Yield models, wafer-map signatures, Pareto charts, SQL and Python

What a two-week learner can credibly target

Two weeks will not make you a device physicist or an analog designer; those roles expect a degree in the field and years of depth. It is enough to interview credibly where your other strengths count: applications and FAE roles at power and microcontroller companies (TI, Infineon, ST, NXP, Microchip, onsemi, Wolfspeed), especially where EV and charging experience matters; product and test engineering, where Python and automation carry over to ATE and data work; yield and data roles that need SQL and statistics; and EV powertrain or charger hardware roles that select SiC and GaN parts. Lead with what you have built, and connect it to their products.

Interactive: explore the map and trace a chip

The semiconductor value chain

Click any box for its companies, roles and interview topics. Press Play to trace one chip from design to a finished product.

Press Play to follow one smartphone chip through the industry.

Fabless

Designs chips and owns the customer, then pays a foundry and an OSAT to build them.

NVIDIAQualcommAMDAppleBroadcomMediaTek

Numbers and facts

AMD went fabless in 2009 when it spun its fabs out as GlobalFoundries.
A leading-edge SoC takes two to three years and hundreds of engineers from spec to tape-out.

Roles here

Digital design (RTL)
Design verification
Physical design and timing
Analog and mixed-signal design
Applications and field applications engineering

Interview topics

Write a FIFO or state machine in Verilog
Clock-domain crossing
Setup and hold timing
Debug a customer's board

Trace a chip

In practice

Practice

Write a two-sentence pitch for an applications-engineer role

You are coming from EV charging and software, applying for a SiC applications-engineer role at a power semiconductor company. Write two sentences: the first proves you have done relevant work, with a number; the second says what you will do for their customers with their products. Then compare with the worked answer and the checklist.

text

Template
  1) I have <built/shipped X> where I <did the hardware or debug part>, <number>.
  2) I want to bring that to <their product line>, helping <their customers>
     <do something faster or better> because I have <shared context>.

Worked answer
  1) For the last four years I have built EV charging sites end to end, specifying
     the power hardware for 150 kW DC chargers, commissioning them and writing the
     software that monitors their faults across more than 40 stalls.
  2) I want to bring that to your SiC applications team, helping charger and
     inverter makers design your MOSFETs in and debug their first boards, because I
     have been the customer who needed exactly that support.

Checklist (the worked answer passes all four)
  [x] a specific system and a number (150 kW, 40 stalls, four years)
  [x] names their product (SiC MOSFETs) and their customer (charger makers)
  [x] says what you will do (design-in support, board debug), not what you want
  [x] makes no claim you could not defend in a follow-up question

Expect the follow-up “tell me about a time you debugged a power-hardware problem,” and have one story ready with a measurement, a root cause and a fix.

Real-world scenario

Interview case: “Our part fails in the field at high temperature. What do you do?”

Final-round interview for an applications-engineer role at a power-semiconductor company. The hiring manager says: an automotive customer reports 120 ppm field failures of our 40 V gate-driver IC, all in vehicles in hot climates, and the returned parts pass test at room temperature. Walk me through what you would do.

Symptoms

Field returns cluster in Arizona and the Gulf states, and failures appear only when under-hood temperature exceeds about 105 °C.
Returned parts pass the full final test at 25 °C but show 3× the datasheet leakage on one pin when retested at 125 °C.
Every failing part comes from two date codes assembled at one OSAT site.

Interview questions

screenExplain the difference between fabless, foundry and IDM.

A fabless company, such as NVIDIA or Qualcomm, designs chips and owns the customer but pays a foundry to make them. A foundry, such as TSMC, manufactures wafers for many customers and does not sell its own chip designs. An IDM, such as Texas Instruments or Infineon, does both: it designs, fabricates and usually tests its own products. The lines are blurring: Intel now runs Intel Foundry for outside customers, and TSMC does advanced packaging that used to be OSAT work.

screenWhat does an applications engineer do?

An applications engineer is the bridge between a chip and the customers designing it into products. Day to day that means writing reference designs and application notes, answering design questions, reviewing customer schematics and layouts, and debugging boards in the lab when something does not work. They also carry customer requirements and failure reports back to the product and design teams. It suits someone who likes hands-on hardware debug as much as explaining things clearly.

screenWhy are ASML and TSMC so strategically important?

ASML is the only company that makes EUV lithography scanners, which every chip at 7 nm-class and below depends on, and each costs around $200 million. TSMC manufactures most of the world's leading-edge logic, including chips for Apple, NVIDIA, AMD and Qualcomm. That concentration means export controls on ASML tools, or any disruption in Taiwan, touches almost every advanced product. It is also why the CHIPS Act paid to build leading-edge fabs in the United States.

deepOur part fails in the field at high temperature. What do you do?

First I would gather data and contain: failure rate in ppm, lot and date codes, the application and mission profile, and the failure signature, and I would hold suspect inventory. Then I would verify the failure on returned parts at the field condition, for example a hot test at 125 °C, next to known good parts. Next come non-destructive steps such as X-ray and acoustic microscopy, then electrical fault isolation with curve tracing and thermal or emission imaging, and only then decapsulation and cross-sections to find the physical defect. Finally I would document root cause, corrective action and verification tests in an 8D report, and check whether other products share the same risk.

deepHow has Moore's law changed, and what drives progress now?

Gordon Moore observed in 1965 that component counts were doubling every year, and in 1975 revised it to about every two years, which held for decades: the Intel 4004 had 2,300 transistors in 1971 and Apple's M1 had 16 billion in 2020. Dennard scaling, which kept power density constant as transistors shrank, ended around 2005, so clock speeds stalled near 3-5 GHz. Progress now comes from new transistor structures like FinFET and gate-all-around, EUV lithography, specialised accelerators, and advanced packaging with chiplets and HBM. Node names such as 3 nm are now labels rather than any physical dimension.

References and further reading

Where the ideas in this lesson come from, and what to read next. Books are the standard texts; papers are the original sources; standards are what employers work to.

Book
Chris Miller (2022). Chip War: The Fight for the World's Most Critical Technology. Scribner.
Read: The whole book; it reads like a thriller and gives you the industry map.
Paperfree online
Gordon E. Moore (1965). Cramming More Components onto Integrated Circuits. Electronics 38(8), 114-117.
Read: Read the original before quoting Moore's law in an interview.

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