PCB Design

Practical: design the robot's motor-driver board in KiCad

A complete KiCad workflow from schematic to a fab order for the course robot's driver board.

Day 6 · 60 min

After this lesson

You can take a design from schematic to Gerbers in KiCad.
You can set up a stack-up and design rules and pass DRC.
You can order a board and an assembly from a low-cost fab.

What we are building, and why it is laid out this way

This is the lesson where you build the board. The target is the robot's motor-driver board: 60 × 40 mm, four M3 holes, an ESP32-WROOM-32, a TB6612FNG dual H-bridge, a 3.3 V regulator, two motor connectors, an HC-SR04 header, two line-sensor headers and a protected battery input. Everything from the last lessons is used here: loops, decoupling, stack-up, DFM, and the bring-up that follows.

The circuit

Ref	Part	Role
J1	JST XH 2-pin	2S battery input, 6.0 to 8.4 V
Q1, R1	AO3401A P-FET, 100 kΩ	Reverse-polarity protection, drain to the connector
C1, C2, C3	100 µF, 10 µF, 100 nF	VM bulk and ceramics at the TB6612FNG
U3, C5	AMS1117-3.3, 22 µF tantalum	3.3 V regulator and its output capacitor
U1, C6, C7	ESP32-WROOM-32, 10 µF, 100 nF	Module and its 3V3 decoupling
U2, C4	TB6612FNG, 100 nF	Dual H-bridge, 1.2 A average per channel
J2, J3	JST PH 6-pin	Motor and encoder connectors
J4, J5, J6, J7	1×4, 1×3, 1×3, 1×4 headers	HC-SR04, two line sensors, UART for programming
SW1, SW2, R2, C8	Tactile switches, 10 kΩ, 1 µF	BOOT on IO0, EN with its pull-up and delay
D1, R3	LED 0603, 1 kΩ	Status LED on IO13
H1 to H4	M3 holes, 3.2 mm	3.5 mm from each corner

The power path

A 2S Li-ion pack enters J1 and passes Q1. Its drain faces the connector, its source feeds the board and its gate sits at ground through R1. With the pack the right way round the FET turns on and drops about 50 mΩ × 3 A = 0.15 V; connect the pack backwards and the gate sees no voltage below its source, so the FET stays off and its body diode blocks. The VM rail feeds the TB6612FNG (4.5 to 13.5 V, 1.2 A average and 3.2 A peak per channel) and the AMS1117-3.3. That regulator burns (8.4 − 3.3) × 0.15 A = 0.77 W at a full pack and 150 mA, about a 46 °C rise at 60 °C/W (the datasheet gives 15 °C/W junction to tab and 46 to 90 °C/W to ambient for a SOT-223, depending on the copper), so its tab gets a copper pour; a buck module is the upgrade for heavy Wi-Fi use.

Pins and strapping

Nets	ESP32 pins	Goes to
PWMA, AIN1, AIN2	IO25, IO26, IO27	TB6612FNG channel A
PWMB, BIN1, BIN2, STBY	IO18, IO19, IO23, IO4	Channel B and standby
Encoders A and B, two motors	IO34, IO35, IO36, IO39	J2 and J3 (input-only pins)
LINE_L, LINE_R, TRIG, ECHO	IO32, IO33, IO16, IO17	J5, J6 and J4

Keep the strapping pins (IO0, 2, 5, 12, 15) away from anything driven at reset, and remember that IO34 to IO39 are input-only. The line sensors sit on ADC1 pins because ADC2 stops working while Wi-Fi runs. The classic HC-SR04 wants 5 V and returns a 5 V ECHO that would damage a 3.3 V GPIO. This board only has a 3.3 V rail, so fit an HC-SR04P, which the header can power, or run a classic one from a separate 5 V source and divide ECHO with 1 kΩ and 2 kΩ.

Stack-up and rules

Order four layers at the fab's standard 1.6 mm stack-up (JLC04161H-7628 at JLCPCB): L1 parts and signals, L2 solid GND, L3 power pours for VM and 3V3, L4 signals and GND. The prepreg between L1 and L2 is 0.21 mm, so every return current runs 0.21 mm below its trace, the loop-area win from the integrity lesson. Rules, with margin over the fab's minimums: 0.2 mm clearance and track, 0.6/0.3 mm vias, 0.15 mm annular ring, 0.3 mm copper to edge. Net classes: Default 0.2 mm, Power 0.5 mm, Motor 1.5 mm for VBAT, VM and the four motor outputs. IPC-2221 gives 1.37 mm for 3 A at a 10 °C rise on 1 oz outer copper, so 1.5 mm is comfortable even with both motors stalled.

Placement plan

Think in zones. The motor driver, its bulk capacitor and the motor connectors share the top-left so the motor current loop is short. The battery connector, Q1 and the regulator sit at the bottom-left, so power enters beside its biggest user. The ESP32 takes the right side with its antenna end at the board edge over a copper keep-out, and the headers line the front edge. Decoupling goes within 3 mm of each power pin with its ground via at the pad, the 100 µF bulk capacitor within 5 mm of the VM pins, and the M3 holes get a 6.4 mm keep-out for screw heads and washers.

Heat and copper

Count the watts before you route. At 1 A per channel the TB6612FNG dissipates about 2 × 1² × 0.5 Ω = 1 W, which on a small SSOP-24 with a thermal resistance of roughly 100 °C/W or worse would mean a rise of 100 °C or more. Put the part on a ground pour with a few 0.3 mm thermal vias down to L2 and keep the motor currents modest. Q1 dissipates 0.45 W at 3 A and the regulator 0.77 W. None of these is a problem alone; together in one corner of a small board they are, which is why the placement spreads them out.

Ground, returns and the frame

L2 stays an unbroken ground plane: no slots under the control bus, and the motor return runs from the driver to the battery connector over it, not through the logic corner. Treat the enclosure as a constraint from day one. Import the chassis drawing as a reference layer and take the outline and hole positions from it, because DRC will happily pass a board that does not fit.

Placement plan with zones. The motor current stays in the top-left loop, logic and the antenna sit on the right, and the sensors face forward. Part boxes include their pads.

Interactive: from schematic to layout

Drag the slider or press play. Watch the symbols become footprints, the footprints grow a ratsnest, the ratsnest turn into copper one net at a time and the board end up poured with ground.

From schematic to layout: the five stages of a KiCad board

Scrub the slider (or press play) to watch the robot's driver board go from schematic symbols to footprints, a ratsnest, routed copper and a ground pour. Only the key nets are drawn.

Design progress0 %, 1. Schematic

Jump to stage

1. Schematic

Symbols and net names. ERC is clean: every input is driven, power flags are in place, and the control buses connect by label rather than by wire.

footprints placed 0 / 29 · unrouted connections not shown yet

The workflow, step by step in KiCad 9

Project. In the Project Manager choose File, New Project, name it robot-motor-driver and keep Create a new folder ticked. Put the folder under git. You get a .kicad_pro, a .kicad_sch and a .kicad_pcb.
Schematic sheet. Open the Schematic Editor and set File, Page Settings: A4, title, revision A and the date.
Symbols. Press A and add RF_Module:ESP32-WROOM-32, Regulator_Linear:AMS1117-3.3, Transistor_FET:AO3401A, the TB6612FNG (search the symbol chooser for TB6612), Device:R, C, C_Polarized and LED, Switch:SW_Push, Connector_Generic headers and Mechanical:MountingHole. Add power symbols with P.
Wires and labels. Wire the power path (W), label the control nets with L (PWMA, AIN1 and so on), add a PWR_FLAG on VBAT, VM and GND, and put no-connect flags (Q) on unused module pins.
Annotate and ERC. Tools, Annotate Schematic; then Inspect, Electrical Rules Checker. Fix every error and read every warning.
Footprints. Tools, Assign Footprints: 0402 for small passives, 0805 for the 10 µF, SOT-223-3_TabPin2 for the AMS1117, SOT-23 for Q1, the 3216 tantalum, SSOP-24 for the TB6612FNG, RF_Module:ESP32-WROOM-32, JST XH and PH connectors and MountingHole_3.2mm_M3. Check each against the datasheet. Add an LCSC field with the supplier part numbers.
Update the board. Open the PCB Editor and press F8, Tools, Update PCB from Schematic. The footprints arrive in a pile.
Board setup. File, Board Setup: four copper layers; Physical Stackup with 35 µm outer copper, 0.2104 mm prepreg, 15.2 µm inner copper and a 1.065 mm core; Constraints from the fab sheet; Net Classes Default, Power and Motor assigned by net name; and the custom rules below.
Outline and holes. Draw a 60 × 40 mm rectangle on Edge.Cuts with 2 mm corner radii, place four MountingHole_3.2mm_M3 at 3.5 mm from each corner and set Place, Drill/Place File Origin at the bottom-left corner.
Placement. Grid 0.5 mm. Put connectors on the edges, the module with its antenna at the right edge, U2 beside C1 and the decoupling at each pin. Add the antenna keep-out with Place, Rule Area (Keepout: copper, tracks, vias, footprints, all layers). Lock the connectors and holes. Check the ratsnest is short.
Routing. Press X for the interactive router. Route VM and the motor outputs first at 1.5 mm, then 3V3, then the control bus at 0.2 mm with 45° bends. Keep signals on L1 and L4 and use 0.6/0.3 mm vias.
Zones. Draw GND zones with Ctrl+Shift+Z on L2 (solid), L1 and L4 with thermal-relief spokes of 0.3 mm, and power pours on L3. Press B to fill all zones and add stitching vias every 5 to 10 mm.
3D check. View, 3D Viewer (Alt+3): connector orientation, the tall capacitor, module direction.
DRC. Inspect, Design Rules Checker with Test for parity between PCB and schematic ticked. Zero errors, and read every warning.
Outputs. File, Fabrication Outputs, Gerbers for F.Cu, In1.Cu, In2.Cu, B.Cu, F.Paste, B.Paste, F.Silkscreen, B.Silkscreen, F.Mask, B.Mask and Edge.Cuts, with Use drill/place file origin and Check zone fills before plotting ticked. Then Drill Files (Excellon, millimetres), Component Placement (CSV, millimetres, SMD only, drill/place origin) and the BOM. A KiCad 9 jobset can store the whole recipe.
Look at what you made. Open the Gerbers in a viewer: closed outline, drills inside the pads, layers in the right order.
Order. At JLCPCB choose four layers, 1.6 mm, 1 oz outer copper, quantity 5. Turn on assembly (top side), upload the BOM and the position file with its columns renamed Designator, Mid X, Mid Y, Layer and Rotation. Open the placement preview and fix rotations, read the DFM report, then pay.

robot-motor-driver.kicad_drutext

(version 1)

(rule "Copper to edge, fab minimum 0.3 mm"
  (constraint edge_clearance (min 0.3mm)))

(rule "Smallest drill, fab minimum 0.3 mm"
  (constraint hole_size (min 0.3mm)))

(rule "Hole to hole"
  (constraint hole_to_hole (min 0.5mm)))

(rule "Silkscreen clear of pads"
  (constraint silk_clearance (min 0.15mm)))

In practice

Practice

Build it in KiCad, then submit it to the fab's DFM check

Do the whole flow yourself with the circuit above, then run this self-review. Do not order until every line is true and the DFM report has been read line by line.

ERC has zero errors and every warning is understood; PWR_FLAGs sit on VBAT, VM and GND.
Every footprint was checked against its datasheet; the polarity marks of C5, D1 and Q1 match the symbols.
No driver or sensor signal uses a strapping pin; IO34 to IO39 are inputs only.
The stack-up, design rules and net classes match the fab, and the custom rules file is loaded.
The antenna keep-out covers every layer and the module sits at the edge.
The 100 µF capacitor is within 5 mm of the VM pins, and every decoupling capacitor is within 3 mm of its pin with a via at its pad.
The motor return path is short and over the ground plane, away from the analog inputs.
No acute copper corners, thermal reliefs on pour pads, silkscreen at least 1 mm tall and clear of pads, with the board name and revision.
DRC reports zero errors with the schematic parity check on.
The 3D viewer shows connector orientation and heights that fit the chassis, and any chassis DXF is imported.
The Gerbers look right in a viewer and the position file origin matches the drill origin.
The assembler's placement preview shows pin 1 and polarity correct on every polarised part.

Finally upload to the fab and submit the board to its DFM check.

Worked answer

A good result is a zip of about 14 files (11 Gerbers, two Excellon drill files and a job file) for a 60 × 40 mm, four-layer, 1.6 mm board, with zero DFM errors. Typical messages and your answer to each:

Hole below the minimum size: a via or thermal via under 0.3 mm. Enlarge it, or order the tier that allows 0.2 mm.
Silkscreen over a pad: move the text 0.15 mm clear or let the fab clip it, then check the legend is still readable.
Copper too close to the edge: pull the pour and any trace back to 0.3 mm and refill the zones.
Mask web too narrow: on 0.65 mm pitch pads with 0.4 mm pads, a 0.05 mm expansion leaves 0.15 mm, so a warning means the mask expansion is larger than you think.
Rotation wrong in the assembly preview: C5's stripe is on the wrong side. Rotate that part 180° in the preview and note the offset for the next order.
Part out of stock: choose an equivalent with the same footprint and update the BOM; if the land pattern differs, change the footprint.

Real-world scenario

DRC passes but the board does not fit the chassis

The motor-driver board passes KiCad DRC with zero errors and the fab's DFM check, and five boards arrive. In the 3D-printed chassis two of the four M3 holes miss their standoffs by 1.5 mm, the JST motor connectors hit the rear wall, and the 5.4 mm tall bulk capacitor collides with the battery tray lid. The chassis designer had emailed a DXF with the pocket outline and the standoff positions weeks earlier.

Symptoms

Zero DRC errors and zero DFM warnings on the order page
Two of the four M3 holes sit 1.5 mm away from the chassis standoffs
J2 and J3 touch the rear wall when the board is lowered in
The 100 µF capacitor, 5.4 mm tall, hits the battery tray lid

Interview questions

screenWalk me through your process from schematic to Gerbers in KiCad.

I start with the schematic: place symbols, connect or label the nets, add power flags, annotate and run ERC until it is clean. Then I assign footprints, check each against the datasheet's land pattern and push everything to the board with Update PCB from Schematic. In the board editor I set the stack-up and design rules from the fab's capability sheet, draw the outline, place parts by zone, route power first and then signals, fill the ground zones and run DRC to zero errors. Finally I plot Gerbers and drills, export the position file and BOM, check them in a viewer and submit them to the fab's DFM check.

screenWhat do ERC and DRC check, and what do they not check?

ERC runs on the schematic and checks electrical consistency: unconnected pins, outputs driving each other, power inputs with no source and missing flags. DRC runs on the board and checks copper clearances, track widths, drill sizes, annular rings, copper-to-edge distance and zone connectivity against the rules you set. Neither knows whether the circuit works, whether a footprint matches the real part, or whether the board fits its enclosure. Those need a design review, a datasheet check and a mechanical check.

deepHow do you set up design rules in KiCad for a specific fab?

I read the fab's capability sheet and enter its numbers in Board Setup, Design Rules, Constraints: minimum clearance, track width, annular width, via and drill sizes and copper to edge. I choose my defaults with margin above those minimums, then define net classes, for example 0.2 mm default, 0.5 mm power and 1.5 mm motor, assigned by net-name patterns. For limits the dialog cannot express I add custom rules in the project's .kicad_dru file, such as a minimum hole size or edge clearance. I also enter the fab's stack-up so thickness and impedance are right, and I rerun DRC after every change.

deepHow did you size the motor traces and place the bulk capacitor on the driver board?

For 3 A on a 1 oz outer layer with a 10 °C rise, IPC-2221 gives about 1.4 mm, so VM and the motor outputs use a 1.5 mm net class; the TB6612FNG's pads are narrower, so the traces neck down only at the pads. The 100 µF bulk capacitor goes within 5 mm of the VM pins with a 10 µF and a 100 nF beside it, so the inrush and the PWM edges are supplied locally. The motor return current gets a short, direct path back to the battery connector over a solid ground plane. I check it against the loop-area idea: short, wide and close to the plane.

screenWhich files go to the fab and to the assembler for a KiCad project?

The fab gets Gerbers for every copper, mask, silkscreen, paste and outline layer plus the Excellon drill files, normally in one zip. The assembler additionally gets the BOM with supplier part numbers and the position file with reference, X, Y, rotation and side. KiCad exports these from File, Fabrication Outputs, and KiCad 9 can save the whole set as a jobset so it is repeatable. Before ordering I open the Gerbers in a viewer and check the assembler's placement preview for rotation and polarity.

deepA board passes DRC but does not fit its enclosure. What do you change in your process?

DRC only checks the board file, so I bring the mechanical constraints into it. I import the chassis DXF onto a user layer, take the outline and hole positions from it, and add keep-out areas for standoff heads, walls and tall neighbours. I place the connectors with that layer visible, review heights in the 3D viewer and export STEP to check against the enclosure model. For a first article I also print the outline at 1:1 and test-fit it before ordering.

References and further reading

Where the ideas in this lesson come from, and what to read next. Books are the standard texts; papers are the original sources; standards are what employers work to.

Documentationfree online
Espressif Systems (2025). ESP32 Hardware Design Guidelines: Schematic Checklist. docs.espressif.com.
Read: EN pull-up, strapping pins and decoupling for U1.
Documentationfree online
Toshiba (2014). TB6612FNG: Driver IC for Dual DC Motor (datasheet). toshiba.semicon-storage.com.
Read: The ratings quoted for U3 and the VM range.
Documentationfree online
Advanced Monolithic Systems (2012). AMS1117: 1A Low Dropout Voltage Regulator (datasheet). advanced-monolithic.com (free PDF at advanced-monolithic.com/pdf/ds1117.pdf, http only).
Read: Thermal resistance figures behind the copper pour under U3.
Documentationfree online
The KiCad Team (2025). KiCad Documentation. docs.kicad.org.
Read: The Getting Started tutorial and the PCB editor manual.
Documentationfree online
David Haboud, Altium (2016). Getting Started with PCB Design. Altium tutorial, 29 pages.
Read: The same project flow in Altium Designer, step by step with screenshots.
Documentation
Altium Limited (2002). P-CAD 2002 PCB User's Guide. Altium, 620 pages.
Read: Chapter 4, the tutorial design session, for a second worked layout.
Standard
IPC (2012). IPC-2221B: Generic Standard on Printed Board Design. IPC.
Read: The rules you type into the design-rule editor.

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Key terms

ERC (electrical rules check): A schematic-level check for electrical inconsistencies: unconnected pins, two outputs driving one net, power inputs with no source, missing power flags. It does not know whether the circuit works.
DRC (design rules check): A board-level check of copper clearances, track widths, drill sizes, annular rings, copper-to-edge distance and zone connectivity against rules you set. It knows nothing about the enclosure.
Update PCB from Schematic (F8): The KiCad action that pushes the netlist, footprints and net names from the schematic into the board. Run it again after every schematic change to keep the two in step.
Footprint: The land pattern of a part on the board: pads, silkscreen outline and courtyard. It must match the real part's datasheet, and a wrong footprint is the most expensive mistake in a first spin.
Net class: A named group of nets that share design rules such as track width, clearance and via size. In KiCad 9 nets are assigned to classes by name patterns, so VM and the motor outputs can be 1.5 mm while signals stay at 0.2 mm.
Stack-up: The ordered list of copper and dielectric layers with their thicknesses. A typical four-layer 1.6 mm board has 35 µm outer copper, 0.21 mm prepreg, a 1.065 mm core and 15 µm inner copper.
Rule area (keep-out): A drawn region that forbids copper, vias, tracks or footprints. It is used under an antenna, around standoff heads and wherever the enclosure needs clearance.
Zone (copper pour): A filled copper area tied to a net, usually GND. Thermal-relief spokes connect its pads, stitching vias tie layers together, and it must be refilled after edits.
Ratsnest: The thin straight lines drawn between pads that share a net but are not yet routed. Short, untangled lines mean a good placement.
Position (centroid) file: The CSV that tells the assembler each part's reference, X, Y, rotation and side. Its origin must match the drill and place origin set in the board.
PWR_FLAG: A schematic symbol that marks a net as driven by a power source, which silences ERC's power-input-not-driven error on rails fed by connectors or regulators that KiCad cannot see as outputs.
Jobset: A KiCad 9 feature that stores a recipe of fabrication outputs (Gerbers, drills, position file, BOM) so they can be regenerated identically with one command.