Semiconductors

CMOS logic: from gates to chips

The CMOS inverter, dynamic power, memory types and what a 3 nm node actually means.

Day 2 · 50 min

After this lesson

You can draw a CMOS inverter and NAND gate and explain why CMOS burns almost no static power.
You can compute dynamic power from P = αCV²f and explain DVFS.
You can compare SRAM, DRAM and Flash and describe FinFET and gate-all-around transistors.

From one inverter to tens of billions of transistors

CMOS, complementary MOS, pairs n-channel and p-channel MOSFETs. In the simplest gate, the inverter, a PMOS connects the output to the supply VDD and an NMOS connects it to ground, and one input drives both gates. Input high: the NMOS turns on, the PMOS turns off and the output is pulled to 0 V. Input low: the PMOS turns on, the NMOS turns off and the output is pulled to VDD. In either steady state one transistor is off, so there is no DC path from supply to ground: a CMOS gate holding a value draws only leakage. Frank Wanlass of Fairchild filed the patent in 1963, and by the late 1980s CMOS had replaced NMOS and bipolar logic almost everywhere.

A CMOS inverter: the schematic (left) and the same circuit in silicon (right). The NMOS sits in the p-type substrate, the PMOS in an n-well; the input drives both gates and the output joins both drains.

Where the power goes

Power is spent when outputs switch. Charging a load capacitance C (the next gates' inputs plus wiring, around 1 fF per gate in a modern process) from 0 to VDD draws energy C·VDD² from the supply: half is stored and half burns in the PMOS, and the stored half burns in the NMOS on the way back down. Averaged over a chip, P = α · C · V² · f, where C is the total switchable capacitance, f the clock and α the activity factor, the fraction of capacitance that charges each cycle (0.05-0.2 for logic, 1 for the clock tree). A brief short-circuit current while both transistors are partly on adds about 10%, and leakage adds static power that climbs with temperature.

The square makes voltage the strongest knob. Maximum clock frequency is roughly proportional to voltage, so lowering both by 10% cuts dynamic power by about 27% (0.9³ = 0.73). That is dynamic voltage and frequency scaling (DVFS): phones and laptops drop to 0.6-0.7 V when lightly loaded and raise voltage only for bursts.

NAND, NOR and sequential logic

Every CMOS gate is a pull-down network of NMOS transistors plus the mirror-image pull-up network of PMOS. A 2-input NAND has two NMOS in series (the output goes low only when both inputs are high) and two PMOS in parallel: four transistors. NOR swaps the arrangement. Designers prefer NAND because the slower PMOS devices sit in parallel rather than in series, and NAND alone can build any logic function.

Combinational logic, such as adders and multiplexers, computes outputs from current inputs only. Sequential logic adds memory: a D flip-flop of about 20 transistors captures its input on a clock edge and holds it until the next. A synchronous design moves data from flip-flop to flip-flop once per clock period, 333 ps at 3 GHz, and the slowest chain of gates between two flip-flops, the critical path, sets the maximum clock.

From gates to a CPU

Gates make adders; adders, shifters and multiplexers make an arithmetic logic unit (ALU); add registers, instruction decode and control and you have a processor. The Intel 4004 of 1971 had 2,300 transistors on a 10 µm process. Apple's M3 Max (2023) has 92 billion and NVIDIA's B200 GPU 208 billion across two dies.

Memory

Type	Cell	Speed	Where and why
SRAM	6 transistors: two cross-coupled inverters plus two access transistors	about 1 ns	Caches and registers; no refresh, but about 0.02 µm² per bit even at 3-5 nm
DRAM	1 transistor + 1 capacitor (1T1C)	tens of ns	Main memory (DDR5, HBM); the charge leaks, so every row is refreshed within 32 ms on DDR5 and HBM (64 ms on DDR4)
Flash	1 floating-gate or charge-trap transistor	tens of µs to read	SSDs and microcontroller program memory; keeps data unpowered for years; 3D NAND stacks 200+ layers

Flash stores charge on an isolated gate, shifting the transistor's threshold voltage; a read checks whether the cell conducts at a chosen gate voltage. Programming pushes electrons through the oxide by tunneling at about 15-20 V, which slowly wears it out: about 1,000-3,000 program-erase cycles for TLC NAND, up to 100,000 for SLC.

What "3 nm" means

Until the late 1990s a node name matched the gate length: a 0.35 µm process had 0.35 µm gates. Since then it is a generation label. TSMC's 3 nm process has a contacted gate pitch around 45-50 nm and a tightest metal pitch around 23 nm; nothing on the chip is 3 nm wide. The meaningful number is density, roughly 1.6× more logic transistors per mm² per full node.

Shape matters as much as size. Below about 30 nm a planar gate, touching the channel only from above, could not turn the transistor fully off because the drain's field leaked into the channel. Intel's 22 nm process (2011) introduced the FinFET, standing the channel up as a fin 5-8 nm wide with the gate on three sides. Gate-all-around (GAA) nanosheets wrap the gate around stacked horizontal ribbons on all four sides: Samsung's 3 nm (2022), then TSMC N2 and Intel 18A (2025). Next comes CFET, stacking the NMOS directly on the PMOS.

TDP and thermal limits

Every watt must leave through the package and cooler. Thermal design power (TDP) is the sustained power a cooler is built for: about 15-45 W for laptop chips, 65-250 W for desktop CPUs, 700 W for an NVIDIA H100 and up to 1,000 W for a B200. Near 100 °C the chip throttles, cutting frequency and voltage. Since Dennard scaling ended around 2005, supply voltages have stayed near 0.7-1 V, because thresholds cannot drop further without leakage exploding (at best 60 mV per tenfold change in subthreshold current at room temperature). Clock speeds stalled at 3-5 GHz, and extra transistors went into more cores, bigger caches and specialised accelerators.

Interactive: switch the gates

CMOS gates: switching costs charge

Toggle the inputs and watch which transistors conduct. Charge flows only when the output actually switches: up from VDD to charge the load, or down to ground to empty it. The scope logs every input change; the bar scales a whole chip's dynamic power with V² and f.

Gate

Clock frequency f3.0 GHzSupply voltage VDD1.00 V

Output: 1 (pulled up to VDD)
Conducting transistors: PMOS on, NMOS off
Static (DC) current: ≈ 0: one network is always off
Last input change: none yet: toggle an input
Chip dynamic power αCV²f: 0.30 W
Supply energy per 0→1 switch, 1 fF load: C·V² = 1.00 fJ

Things to try:

Toggle the inverter input: a tall supply-current spike appears only when the output rises.
In NAND mode, set A = 0 and toggle B: the output never changes, so almost no charge moves. That is what a low activity factor α looks like.
Raise VDD from 1.0 to 1.1 V at 3 GHz: power goes from 0.30 to 0.36 W, the 21% of the scenario below.

In practice

Practice

Truth table of a NAND from its transistors

For a 2-input CMOS NAND (NMOS A and B in series to ground, PMOS A and B in parallel to VDD), work out which transistors conduct for each input pair and what the output is.

text

 A B | NMOS A  NMOS B (series) | PMOS A  PMOS B (parallel) | OUT
 0 0 |  off     off   → open   |  on      on    → closed   |  1
 0 1 |  off     on    → open   |  on      off   → closed   |  1
 1 0 |  on      off   → open   |  off     on    → closed   |  1
 1 1 |  on      on    → closed |  off     off   → open     |  0

Answer: OUT = NOT(A AND B). In every row exactly one network conducts, so there is never a DC path from VDD to ground, which is why the gate draws no static current.

Practice

Dynamic power of a small chip

A chip has C = 1 nF of total switchable capacitance, runs at V = 1 V and f = 3 GHz, and its activity factor is α = 0.1. Compute its dynamic power. Then compute it after a 10% voltage increase at the same clock, and after lowering both voltage and frequency by 10%.

text

P = α · C · V² · f
  = 0.1 × 1e-9 F × (1 V)² × 3e9 Hz   = 0.30 W

V = 1.1 V, f = 3 GHz:   0.1 × 1e-9 × 1.21 × 3e9   = 0.363 W   (+21%)
V = 0.9 V, f = 2.7 GHz: 0.1 × 1e-9 × 0.81 × 2.7e9 = 0.219 W   (−27%)

Answer: 0.3 W at nominal, 0.363 W (+21%) with 10% more voltage, and 0.219 W (−27%) when DVFS lowers voltage and frequency together. The same arithmetic, scaled up to hundreds of nanofarads, is why a desktop CPU lands near 100 W.

Real-world scenario

The chip overheats after a 10% voltage bump

An edge-AI camera runs its neural accelerator at 1.0 GHz from a 0.80 V core rail. A handful of units showed rare bit errors at 85 °C, so a firmware update raised the core rail by 10%, to 0.88 V, across the whole fleet. The thermal design assumed 10 W of chip power (8 W dynamic, 2 W leakage) with 5 °C/W from junction to the 50 °C air inside a sealed enclosure: a 100 °C junction against a 105 °C throttle point.

Symptoms

Within ten minutes of start-up, units in sealed enclosures hit the 105 °C throttle point and the accelerator clock drops from 1.0 GHz to 700 MHz
The dashboard frame rate falls from 30 to about 21 fps
Core-rail current is up about 14% even though the workload and clock frequency are unchanged
Units on an open bench at 25 °C never throttle

Interview questions

screenWhy does a CMOS gate draw almost no static current?

Every CMOS gate has a PMOS pull-up network to VDD and a complementary NMOS pull-down network to ground, driven by the same inputs. For any steady input combination exactly one network conducts, so there is never a DC path from supply to ground. Current flows only while the output switches, to charge or discharge the load capacitance, plus a brief short-circuit pulse while both networks are partly on. The static power that remains is leakage, which in modern nodes can still be a significant share of the total, especially when hot.

screenDraw a CMOS NAND gate and explain why designers prefer NAND to NOR.

A two-input NAND has two NMOS in series from the output to ground and two PMOS in parallel from VDD to the output, so the output goes low only when both inputs are high. A NOR is the mirror image, with the PMOS in series and the NMOS in parallel. Series transistors add resistance, and PMOS devices are already two to three times weaker than NMOS because holes are less mobile, so a NOR needs very wide PMOS to match speeds. NAND puts the series stack on the faster NMOS side, and since NAND alone is functionally complete, standard-cell libraries lean on it.

deepWhere does power go in a modern SoC, and what techniques reduce it?

Dynamic power is αCV²f, the cost of charging capacitance, plus a small short-circuit term, and static power is leakage, which rises steeply with temperature and with lower threshold voltages. The biggest lever is voltage because of the square, so DVFS lowers voltage and frequency together and adaptive voltage scaling trims each part to its own silicon. Clock gating stops the clock to idle blocks, cutting α, and power gating disconnects idle blocks entirely with header switches to remove their leakage. On top of that, designers use multi-threshold cell libraries, putting low-Vt fast cells only on critical paths and high-Vt low-leakage cells everywhere else.

deepCompare SRAM, DRAM and Flash: cell structure, speed, density and volatility.

SRAM stores a bit in two cross-coupled inverters with two access transistors, six transistors in all, so it is fast, about a nanosecond, and needs no refresh, but it is large, about 0.02 µm² per bit at the 3-5 nm nodes. DRAM uses one transistor and one capacitor per bit, which makes it several times denser and cheaper per bit, but the charge leaks, so every row is refreshed every 64 ms and access takes tens of nanoseconds. Flash stores charge on a floating gate or charge-trap layer, so it keeps data for years without power and stacks over 200 layers in 3D NAND, but reads take tens of microseconds, writes need 15-20 V tunneling and each cell survives only thousands of program-erase cycles. That is why a computer uses SRAM for caches, DRAM for main memory and Flash for storage.

screenWhat does '3 nm' mean, and how did transistors change from planar to FinFET to gate-all-around?

Until the late 1990s a node name matched the gate length, but now it is a generation label: TSMC's 3 nm process has a contacted gate pitch around 45-50 nm and no feature that is 3 nm wide. The real story is density and electrostatics. A planar gate controls the channel only from the top, so below about 30 nm the drain's field leaked into the channel and the transistor could not turn fully off. FinFETs, from Intel's 22 nm process in 2011, wrap the gate around a thin fin on three sides, and gate-all-around nanosheets, from Samsung's 3 nm in 2022 and TSMC N2 and Intel 18A in 2025, wrap it on all four sides to keep leakage down as gates shrink further.

References and further reading

Where the ideas in this lesson come from, and what to read next. Books are the standard texts; papers are the original sources; standards are what employers work to.

Standard
JEDEC (2013). JESD235: High Bandwidth Memory (HBM) DRAM. JEDEC.
Read: HBM refresh timing, which matches DDR5.
Standard
JEDEC (2020). JESD79-5: DDR5 SDRAM. JEDEC.
Read: The refresh timing (tREFI, refresh window) behind the memory table.
Paper
Frank M. Wanlass and Chih-Tang Sah (1963). Nanowatt Logic Using Field-Effect Metal-Oxide Semiconductor Triodes. IEEE International Solid-State Circuits Conference, Digest of Technical Papers.doi:10.1109/ISSCC.1963.1157450
Read: Two pages: why complementary pairs draw almost no static current.
Paper
Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu, V. Leo Rideout, Ernest Bassous and Andre R. LeBlanc (1974). Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions. IEEE Journal of Solid-State Circuits 9(5), 256-268.doi:10.1109/JSSC.1974.1050511
Read: The scaling rules and the table of what shrinks with what.
Paper
Digh Hisamoto et al. (2000). FinFET: A Self-Aligned Double-Gate MOSFET Scalable to 20 nm. IEEE Transactions on Electron Devices 47(12), 2320-2325.doi:10.1109/16.887014
Read: The FinFET structure, before gate-all-around replaced it.
Book
Neil H. E. Weste and David Money Harris (2011). CMOS VLSI Design: A Circuits and Systems Perspective. Addison-Wesley, 4th edition.
Read: Chapters on the CMOS inverter, delay and power, and SRAM/DRAM.
Book
Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolić (2003). Digital Integrated Circuits: A Design Perspective. Prentice Hall, 2nd edition.
Read: The dynamic-power derivation behind P = αCV²f.

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