PCB Design

Power integrity, signal integrity and EMI

Return paths, decoupling, impedance, crosstalk and keeping motor noise out of your ADC.

Day 5 · 50 min

After this lesson

You can explain where return current flows and why plane splits hurt.
You can place decoupling capacitors for a small loop area.
You can recognize when a trace is a transmission line and what to do about it.

Where the current really goes

Every signal on a board is a loop. Current leaves the driver, runs down the trace, enters the receiver and must return to where it started. Power integrity, signal integrity and EMI are three views of one fact: the size and shape of that loop decide whether a board is quiet or a small radio transmitter.

Return currents follow the signal

At DC the return current takes the path of least resistance and spreads through the copper. Above roughly 100 kHz inductance wins, and the current takes the path of least inductance, which is the one that encloses the smallest area: straight underneath the trace on the adjacent plane. About 80 % of it flows within three dielectric heights either side of the trace, so with 0.2 mm of prepreg it is a stripe 1.2 mm wide, while on a two-layer board with 1.6 mm of FR-4 it is 9.6 mm wide.

Cut a slot or split in that plane and the return current must detour around its end. The loop area, the inductance and the radiation all jump, and the detour couples noise into neighbours. Never route a fast signal across a gap in its reference plane. If it has to change layers, change between layers that share the same reference, or add a stitching via (or a 100 nF capacitor) within a few millimetres of the signal via.

The same 48 mm trace over a solid plane and over a plane with a 12 mm slot. The return is drawn beside the trace for clarity; it really flows directly beneath it.

Decoupling and loop area

A microcontroller does not draw a smooth current. Each clock edge takes tens of milliamps in a nanosecond or two, and loop inductance fights any change with V = L·di/dt. A 50 mA step in 2 ns is 25 MA/s, so 10 nH (about 10 mm of thin trace) costs 250 mV and 1 nH costs 25 mV. A decoupling capacitor is a local charge reservoir whose real job is to shrink the fast current loop from tens of centimetres to a few millimetres.

So place the 100 nF capacitor first and closest, put its ground via right at the pad, and let the power trace reach the capacitor before it reaches the pin. A capacitor is only a capacitor below its self-resonance, f = 1/(2π√(LC)): 100 nF with 1 nH resonates at 16 MHz, with 10 nH at only 5 MHz, and above that it is an inductor.

PDN impedance in one paragraph

Treat the power distribution network as an impedance that must stay below Z_target = allowed ripple ÷ transient current. For a 3.3 V rail that may move 5 % (165 mV) under a 0.5 A Wi-Fi burst, Z_target is 0.33 Ω. The regulator holds that up to about 100 kHz, bulk capacitors (22 to 100 µF) carry 100 kHz to 1 MHz, 100 nF ceramics carry 1 to 20 MHz, and above that only loop inductance and plane capacitance matter. A 60 × 40 mm plane pair 0.1 mm apart is only about 0.9 nF: planes help above 100 MHz but never replace local capacitors.

Rise time, impedance and termination

Signal integrity is about edges, not clock rates. An edge of rise time tr has content up to about 0.35/tr, so a 1 ns edge reaches 350 MHz even on a 1 MHz signal. A trace becomes a transmission line when its one-way delay exceeds about a sixth of the rise time. FR-4 outer layers delay a signal by about 6 ps/mm, so the critical length is tr ÷ (6 × 6 ps/mm): 28 mm for 1 ns, 8 mm for 0.3 ns and about 140 mm for a slow 5 ns GPIO.

Past that length you control the characteristic impedance and terminate. The targets are 50 Ω single-ended and 90 Ω (USB) or 100 Ω (Ethernet, LVDS) differential. On a four-layer board with 0.21 mm of prepreg a 50 Ω microstrip is about 0.35 mm wide; on a two-layer 1.6 mm board it would need about 3 mm, which is why impedance-controlled boards are usually four-layer. Terminate by matching: a 22 to 33 Ω series resistor at the driver for a point-to-point line, a parallel resistor at the load for a bus, 100 Ω across a differential receiver. Length matching is delay matching: skew = length difference × 6 ps/mm, so 10 mm of mismatch is 60 ps.

Crosstalk

Neighbouring traces couple through mutual capacitance and inductance. Backward crosstalk falls roughly as 1/(1 + (s/h)²), where s is the centre-to-centre spacing and h the height above the plane, so the cheapest cure is a closer plane. The 3W rule (centre spacing of at least three trace widths) contains about 70 % of the field and 10W about 98 %. Keep clocks and motor PWM away from sensitive analog traces, and cross rather than run parallel on adjacent layers.

Loops as antennas

A small loop of area A carrying current I at frequency f radiates E ≈ 2.6×10⁻¹⁴ · f² · A · I / r (SI units). One square centimetre carrying 10 mA at 100 MHz gives about 90 µV/m at 3 m, over half of the 150 µV/m FCC Class B limit. Common-mode current on cables is worse: E ≈ 1.26×10⁻⁶ · f · L · I / r, so just 10 µA on a 0.5 m cable at 100 MHz gives about 210 µV/m and fails. That is why the motor leads are the antenna. Filter where a cable enters the board with a ferrite bead or common-mode choke plus a capacitor, keep a solid plane under every connector, and remember that a shield is only as good as its biggest hole: about 20·log10(λ/2l) dB for a slot of length l.

Partitioning motors from analog

Partition by placement, not by cutting the plane. Put the motor driver, its bulk capacitor and the battery connector in one corner so the motor return current flows straight back to the battery, and put the ADC inputs and line sensors on the far side. Keep one solid ground. For an ADC pin use a 1 kΩ plus 100 nF filter (corner 1.6 kHz), route over unbroken ground away from switching edges, and sample between PWM edges.

Interactive: decoupling and return paths

First move the capacitor away from the pin and watch the benefit disappear, then cut a slit under the trace and read the loop-area tile. Try the 1.6 mm two-layer setting to see why a close plane matters so much.

Decoupling demo: why the capacitor has to be close

An MCU draws current in nanosecond bursts. The loop inductance between the supply and the pin turns each burst into a voltage spike. Move the capacitor away and watch its benefit disappear.

Loop inductance, capacitor to pin4.0 nHMCU current step80 mA

Capacitor value

No local capacitor (25 nH to the regulator)

min 2.93 V, 711 mV peak to peak

dips below the 3.0 V minimum: brown-out risk

100 nF capacitor, 4.0 nH loop

min 3.22 V, 116 mV peak to peak

inside a 5 % (165 mV) ripple budget

Scope cursor 0.0 ns: load 20 mA, no cap 3.30 V, with cap 3.30 V

Rule of thumb: about 1 nH per millimetre of thin trace and about 1 nH per via. The ringing is the loop inductance resonating with the chip's own 5 nF of on-die capacitance.

Return current over a plane, with and without a slit

The signal runs left to right on the top layer. Its return current has to find its way back through the plane. Cut a slit across the trace and watch the loop area and the radiated emission grow.

Slit length, centred on the trace12 mm

Signal edge

Plane distance below the trace

Loop area: 50.4 mm²
Emission vs. no slit: ×5.2 (+14.4 dB)
Return current: detours 6 mm out and back round the end of the slit

Radiated field from a small loop scales with its area, so ×5.2 area is ×5.2 field strength. A capacitor passes the fast return current but blocks DC, so it fixes the fast case only.

In practice

Practice

Find and shrink the loops on the motor-driver board

Rev A of the motor-driver board is a two-layer design with no ground plane under the traces. Its four current loops, measured on the layout as length × spacing between the outgoing and return copper:

Loop	What flows round it	Length × spacing
1	VM loop: battery connector, TB6612FNG VM, PGND, back to the connector	55 mm × 14 mm
2	Motor output loop: OUT pins, motor connector, second wire back	40 mm × 10 mm
3	ESP32 3V3 loop: capacitor, 3V3 pin, GND pin, capacitor	12 mm × 6 mm
4	Line-sensor loop: signal trace and its return to the ADC input	80 mm × 5 mm

Compute the area of each loop.
Rank the loops by how much each would radiate for equal current and frequency, then by which carries the largest di/dt.
Rev B adds a solid ground plane on layer 2, 0.2 mm below layer 1, so loops 1, 3 and 4 close under their own trace. Compute their new areas and the reduction in dB (20·log10 of the area ratio).
What do you do about loop 2?

Check yourself in the demo above: with the plane at 0.2 mm and a 12 mm slit the loop-area tile should read about 50 mm².

Worked answer

Areas: loop 1 is 55 × 14 = 770 mm², loop 2 is 40 × 10 = 400 mm², loop 3 is 12 × 6 = 72 mm², loop 4 is 80 × 5 = 400 mm².
For equal current and frequency emission follows area: loop 1, then loops 2 and 4, then loop 3. The currents are not equal, though. Loop 1 carries amps switched in tens of nanoseconds (the largest di/dt, a few amps in 30 ns), loop 3 carries only tens of milliamps but with 1 to 3 ns edges (the highest frequencies), and loop 4 carries microamps but is a receiving antenna for everything else. Fix 1 and 3 first.
With the plane: loop 1 becomes 55 × 0.2 = 11 mm² (70 times smaller, about 37 dB less), loop 3 becomes 12 × 0.2 = 2.4 mm² (30 times, about 30 dB) and loop 4 becomes 80 × 0.2 = 16 mm² (25 times, 28 dB).
Loop 2 is mostly the cable. Twist the two motor wires so their loop area collapses, keep them short, add 100 nF across the motor terminals, run the OUT traces side by side over the plane, and keep them out of the ADC corner.

Real-world scenario

Robot resets whenever the motors start

The first spin of the motor-driver board runs the ESP32 happily on the bench with the wheels off the ground. Put the robot on the floor and command both motors from standstill, and the ESP32 reboots about one start in three; the serial console prints Brownout detector was triggered. The pack is a partly discharged 2S Li-ion (7.0 V), connected through 20 cm of lead wire. Rev A of the board has only a 100 nF capacitor at the TB6612FNG VM pins and one thin ground trace shared by the driver, the regulator and the module.

Symptoms

Resets only when both motors start from standstill under load; spinning freely never resets
Serial log shows Brownout detector was triggered, followed by a normal boot
A scope on 3V3 at the module shows a dip of about 700 mV lasting 40 µs, starting exactly when the motor PWM turns on
Between the battery negative terminal and the module GND pin, a second probe shows spikes of about 0.9 V on the PWM edges

Interview questions

screenWhat is a return path, and why does it matter on a PCB?

Every signal is a loop: current goes out along the trace and has to come back to its source. At low frequency it takes the least-resistance path and spreads through the copper, but above roughly 100 kHz it takes the least-inductance path, which is directly under the trace on the adjacent plane. The area between the signal and its return is the loop area, and both radiated emissions and noise pickup scale with it. So good layout is mostly about keeping a continuous reference plane under every fast trace.

screenWhere do you place a decoupling capacitor, and why does the distance matter?

As close to the power pin as the footprints allow, with the ground via right at the capacitor pad and the power trace passing the capacitor before it reaches the pin. The capacitor only works while it looks like a capacitor, and the loop inductance sets its self-resonance: 100 nF with 1 nH resonates near 16 MHz, but with 10 nH only near 5 MHz. Above that it is an inductor and the voltage spike is simply L times di/dt. I use a 0402 or 0603 part, one per power pin, and put the smallest value nearest the pin.

deepA high-speed signal has to cross a split in the ground plane. What happens, and what do you do?

The return current cannot cross the gap, so it detours around the end of the slot. That enlarges the loop, adds inductance, couples noise into everything near the detour and raises radiated emissions. The first fix is to avoid the split, by rerouting the signal or removing the cut. If it must cross, I put a stitching capacitor, typically 100 nF, within a few millimetres of the crossing so the fast return current can hop the gap, and I keep the trace on a layer whose reference is continuous.

screenWhen does a trace have to be treated as a transmission line?

When its one-way delay is more than roughly one-sixth of the signal's rise time. FR-4 outer layers delay a signal by about 6 ps per millimetre, so the critical length is about 28 mm per nanosecond of rise time. A 1 ns edge makes a trace over 28 mm a transmission line even if the clock is only 1 MHz, because the edge rate sets the bandwidth, not the clock. Past that length I control the impedance, usually 50 Ω, and terminate the line to stop reflections.

deepA robot resets whenever its motors start. How do you debug it?

I look at the rails first, with a scope triggered on a dip of the 3V3 rail and the probe ground spring on the module's own ground pin, then compare it with VM at the motor driver. If VM sags, the motor inrush is being pulled through the battery lead without local bulk capacitance, and I add 100 µF plus ceramics at the driver. I also check where the motor return current flows; if it shares a trace with the logic ground, I give it its own path back to the battery. Finally I check the regulator's dropout, soft-start the PWM and re-measure under the same start-up.

deepHow do you keep motor noise out of an ADC?

Partition by placement: motor driver, bulk capacitor and battery connector in one corner so the motor current returns straight to the battery, and the ADC inputs far from that loop. I keep one solid ground plane rather than splitting it, so the return current under every analog trace stays continuous. Each analog input gets an RC filter, for example 1 kΩ and 100 nF, the traces stay away from switching edges, and I filter motors at the source with 100 nF across the terminals. In firmware I sample between PWM edges and average several readings.

References and further reading

Where the ideas in this lesson come from, and what to read next. Books are the standard texts; papers are the original sources; standards are what employers work to.

Documentationfree online
Advanced Monolithic Systems (2012). AMS1117: 1A Low Dropout Voltage Regulator (datasheet). advanced-monolithic.com (free PDF at advanced-monolithic.com/pdf/ds1117.pdf, http only).
Read: Dropout voltage: why 3V3 collapses when VM dips to 4.4 V.
Book
Henry W. Ott (2009). Electromagnetic Compatibility Engineering. Wiley.
Read: The chapters on grounding, return currents and decoupling.
Book
Eric Bogatin (2018). Signal and Power Integrity: Simplified. Prentice Hall, 3rd edition.
Read: Chapters on impedance, transmission lines and crosstalk.
Book
Howard Johnson and Martin Graham (1993). High-Speed Digital Design: A Handbook of Black Magic. Prentice Hall.
Read: The chapters on rise time, ringing and termination.
Book
Bruce Archambeault (2002). PCB Design for Real-World EMI Control. Springer.
Read: The measured results on plane splits and loop area.
Book
Mark I. Montrose (2000). Printed Circuit Board Design Techniques for EMC Compliance. IEEE Press, 2nd edition.
Read: The layout-rules checklist.

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Key terms

Return path: The route current takes back to its source to complete the loop. Above about 100 kHz, on a board with an adjacent plane, it flows directly beneath the signal trace because that path has the least inductance.
Loop area: The area enclosed by a signal path and its return path. Radiated emission and magnetic pickup both scale with it, so good layout shrinks loops instead of adding filters.
Decoupling capacitor: A capacitor at a power pin that supplies fast current locally. Its real job is to shrink the high-frequency current loop from tens of centimetres to a few millimetres.
Self-resonant frequency: The frequency 1/(2π√(LC)) above which a capacitor behaves as an inductor. A 100 nF capacitor with 1 nH of loop inductance resonates near 16 MHz; with 10 nH, near 5 MHz.
Power distribution network (PDN): Everything between the regulator and the die: regulator, bulk capacitors, ceramics, planes and vias. Its impedance must stay below Z_target = allowed ripple ÷ transient current at every frequency.
Characteristic impedance (Z0): The ratio of voltage to current of a wave travelling down a transmission line, set by trace width, dielectric height and permittivity. Common targets are 50 Ω single-ended, 90 Ω differential for USB and 100 Ω for Ethernet and LVDS.
Critical length: The trace length beyond which a line must be treated as a transmission line, about one-sixth of the rise-time distance: roughly 28 mm per nanosecond of rise time on FR-4 outer layers.
Crosstalk and the 3W rule: Unwanted coupling between neighbouring traces through mutual capacitance and inductance. Keeping centre-to-centre spacing at three trace widths or more contains about 70 % of the field.
Common-mode current: Current that flows the same way on every conductor of a cable and returns through the surroundings. A few microamps on a half-metre cable can fail a radiated-emissions test.
Stitching via: A via placed beside a signal via that ties the two reference planes together, so the return current can change layers along a short path instead of a long detour.
Ground bounce: The voltage developed across the inductance and resistance of a shared ground path when large, fast currents flow through it. It shifts one part's local ground relative to another's.