Schematic capture: drawing a circuit people can read

Symbols, designators and nets

A schematic is a drawing of connections, not of geometry: symbols stand for parts, wires and labels define nets, and everything else is annotation. Each part gets a reference designator: R resistor, C capacitor, L inductor, D diode or LED, Q transistor, U integrated circuit, J connector, Y crystal, SW switch, F fuse, TP test point. The designator appears on the schematic, in the BOM and on the board silkscreen, so a technician with a multimeter can find C14 without asking anyone. A net is every pin and wire that is electrically one node. A net label names it so it can cross the page without a drawn wire, and two labels with the same name are one net. The danger is a typo: STBY and STNDBY are two nets with one pin each, and nothing looks wrong.

Power symbols such as +3V3 and GND join every symbol of the same name, so supplies need no wires, and a PWR_FLAG tells the checker that a net is driven from off-board. Local labels join nets within a sheet, global labels join them across all sheets, and hierarchical labels tie a net to a pin on the sheet symbol in the parent page. Split any design bigger than one screen into hierarchical sheets such as power, MCU, motor driver and sensors, so a reviewer can read one page in a minute.

Conventions that make a page readable

• Signal flow runs left to right: inputs on the left, outputs on the right.
• Positive supplies sit at the top and grounds at the bottom, and no ground symbol ever points up.
• Draw each decoupling capacitor right next to the IC pin it serves, because the layout will copy that grouping.
• Put critical specs in the value field (100 nF X7R 16 V), not in a note, and name nets for what they do (MOTA_PWM, +3V3).
• Use junction dots only where wires join, avoid crossing wires, and use a label instead.

Net classes and datasheet reference designs

A net class groups nets that share layout rules: Power at 0.5 mm, Motor at 1.5 mm, Signal at 0.2 mm. Assign the classes in the schematic and the router and design-rule check apply the right widths without per-net fiddling. Every IC datasheet has a typical application circuit. Copy it, then read the footnotes, because that is where it says the AMS1117 wants a 22 µF solid tantalum output capacitor to stay stable (its datasheet, under Stability) or that the ESP32's EN pin wants a 10 kΩ pull-up with a 1 µF capacitor (Espressif's hardware design guidelines, schematic checklist). Write down every deviation and why.

Unused and special pins

Every pin needs a defined state in every phase of operation. Unused outputs can stay open, unused inputs get tied, open-drain buses need pull-ups, and strapping pins need the right level at boot: an ESP32 with IO0 low at reset enters its bootloader. An enable pin left floating passes the bench test and fails in the field.

ERC: what it catches and what it cannot

The electrical rules check compares connectivity against a pin-type matrix of inputs, outputs, bidirectional, power inputs, power outputs, passive and open-collector pins. It flags unconnected pins, power inputs that no power output drives, two outputs on one net, duplicate designators, labels that join only one pin, and sheet-pin mismatches. A no-connect flag marks a pin as intentionally open, but only after you have read the datasheet, because an input marked no-connect is a floating input. ERC cannot know your intent: a missing pull-up, a 100 kΩ where you meant 10 kΩ, a connector pinout mirrored left to right and a regulator that cannot supply the load all pass cleanly. Treat every message as a defect until it is fixed or waived with a written reason.

BOM thinking

A bill of materials lists every part with designators, quantity, value, footprint, manufacturer, manufacturer part number (MPN) and supplier number. A value like 100 nF is not enough, because dielectric, voltage rating, tolerance and package all decide whether the part works, so the MPN is the ground truth: for example Murata GRM155R71C104KA88D is 100 nF, 16 V, X7R, 0402. Group identical parts, mark the ones not to be populated, list approved alternates that share the footprint, and check stock and lifecycle before release. A missing alternate has turned into a multi-month delay on more than one product.

Version control

KiCad stores schematics and boards as text, so Git works. Commit each logical change with a message that says why, tag releases such as rev-A together with the exact Gerbers, and keep generated files and backups out of the repository. A schematic you cannot diff is a schematic you cannot review.