PCB Design

DFM and how boards get made

Fab capabilities, Gerbers, reflow profiles, tombstoning and what a DFM check catches.

Day 6 · 50 min

After this lesson

You can list the files a fab and an assembler need and what each contains.
You can describe the fabrication and SMT assembly process steps.
You can explain common DFM violations and how to avoid them.

From Gerbers to a soldered board

Your CAD tool's design rule check (DRC) answers one question: does the board obey the numbers you typed in? Design for manufacturability (DFM) asks a harder one: will a factory build it, at a sensible price, with a high yield? DRC compares geometry with numbers. DFM also looks at process: acid traps, mask slivers, thermal balance, paste volume and panelisation. A board can pass DRC cleanly and still tombstone, so copy the fab's capability sheet into your DRC rules before you route.

What a fab can build

Typical low-cost prototype capabilities (check the current page, the numbers move): trace and space 0.127 mm (5 mil); mechanical drill 0.3 mm, or 0.2 mm on four layers; annular ring 0.15 mm; solder-mask web 0.1 mm; copper to board edge 0.3 mm; silkscreen line 0.15 mm and text 1 mm tall. Design with margin. My defaults are 0.2 mm trace and space and a 0.3 mm drill with a 0.6 mm pad, dropping to the minimum only where a QFN or BGA forces it. Every step tighter costs yield and eventually money.

The files

The fab needs one Gerber (RS-274X) file for each copper layer, solder mask, silkscreen and paste, one for the board outline, and an Excellon file for drills. A single IPC-2581 or ODB++ package can carry all of that plus the stack-up and netlist. The assembler also needs a bill of materials (BOM) with supplier part numbers, a centroid file giving each reference designator's X, Y, rotation and side, and an assembly drawing with polarity marks. Rotation conventions differ between CAD tools and assembly houses, so always inspect the assembler's placement preview for diodes, tantalum capacitors and ICs.

How the bare board is made

Imaging: photoresist on 35 µm copper-clad laminate is exposed with your artwork, inner layers first.
Etching removes the unprotected inner-layer copper, and automated optical inspection checks each inner layer.
Lamination presses the layers and prepreg together at about 180 °C.
Drilling cuts the holes: mechanical down to 0.2 mm, laser for microvias.
Plating puts about 20 µm of copper in the barrels so the holes connect layers.
The outer layers are imaged and etched only now, after plating, with tin protecting the copper that stays.
Solder mask, a liquid photoimageable ink, is printed and exposed, leaving the pads open.
Legend: silkscreen text is printed by inkjet.
Surface finish (HASL, ENIG gold over nickel, or OSP) protects the exposed copper.
E-test: a flying-probe tester checks every net for opens and shorts.

Surface finish matters for assembly. HASL is cheap but leaves uneven domes that are bad under fine-pitch parts. ENIG is flat and keeps well, which is why QFNs and BGAs want it. OSP is flat and cheapest but has a short shelf life once the bag is opened.

A SAC305 reflow profile. The shaded area is the time above the 217 °C liquidus; the solder only wets while it is liquid.

How it is assembled

A laser-cut stainless stencil, about 0.12 mm thick, lets a squeegee print solder paste on every pad; paste is roughly 50 % metal by volume. A pick-and-place machine then sets each part onto the paste to about 0.05 mm. Reflow melts the paste along a profile for SAC305: ramp at 3 °C/s or less, soak at 150 to 200 °C for 60 to 120 s, peak at about 245 °C with 45 to 90 s above 217 °C, cool at 4 to 6 °C/s at most. Through-hole parts are soldered afterwards by wave (about 260 °C for 2 to 4 s) or selectively. Automated optical inspection checks every joint, and X-ray looks under BGAs and QFN thermal pads.

Stencil design is half of paste printing. An aperture needs an area ratio (opening area divided by wall area) of at least 0.66 and an aspect ratio (width divided by stencil thickness) of at least 1.5, or the paste stays on the walls. A 0.2 × 0.6 mm aperture for a 0.4 mm pitch QFN passes at 0.1 mm thickness (ratio 0.75) but fails at 0.12 mm (0.63), which is why fine-pitch boards use thinner stencils and Type 4 powder.

Classic pitfalls

Tombstoning: one pad melts first and its surface tension lifts the part. Balance the copper on both pads and use thermal relief on pour connections.
Bridges: mask webs under 0.1 mm or too much paste short fine-pitch pins. Keep mask dams and shrink stencil apertures by about 10 %.
Acid traps: acute copper angles hold etchant. Keep junctions at 90° or use 45° chamfers.
Fiducials and rails: three 1 mm fiducials per board, and 5 mm panel rails with tooling holes, let the line align and carry the boards. Keep tall parts 3 mm from the rails.

Small boards ship in panels. V-score cuts a groove from both sides and snaps apart, but needs parts and copper about 0.4 mm back from the cut. Tab routing with perforated mouse bites allows odd outlines. Either way, keep ceramic capacitors away from the break line, because flexing a board cracks them and a cracked capacitor becomes a short.

What drives the price

Layer count (each step up roughly doubles the board price), board area, quantity, smallest drill and trace, finish (ENIG over HASL) and impedance control set the bare-board cost. For assembly it is the number of unique parts, BGA or double-sided placement and the one-off stencil and set-up fees. A five-board run is dominated by fixed costs, so reusing common parts matters more than shaving a square centimetre.

DFM at compile time

AI design pipelines turn the same idea into a compiler pass: the generator proposes geometry, an automated checker applies the fab's rules, and violations return as errors until the design compiles. You can do this for a PCB today by running kicad-cli pcb drc in CI with the fab's rules and failing the build on any violation.

Interactive: watch a board get assembled, then check it

Step through the assembly line, then set the reflow profile yourself and see when SAC305 wets, balls up or overheats. Afterwards run the same tiny layout through a DRC-style check and a fab-style check.

SMT assembly: stencil, paste, place, reflow, inspect

Step through the five stages one board goes through on an assembly line. At the reflow step, set the peak temperature, ramp and dwell and see when SAC305 wets, balls up or overheats.

Step 1 / 5

Stencil

A laser-cut stainless-steel stencil, about 0.12 mm thick, is aligned over the board and a squeegee pushes solder paste through its apertures. Apertures must have an area ratio of at least 0.66 and an aspect ratio of at least 1.5, or the paste sticks to the walls instead of the pad.

Cross-sections are not to scale (a real pad is 35 µm thick). On a prototype line the stencil print takes about 20 s, placement 0.5 to 2 s per part and reflow 4 to 6 minutes door to door.

DFM checker: the same tiny layout against three sets of numbers

Toggle checks on and watch violations light up. Start with the four checks a CAD DRC runs, then switch on the three that normally need the fab's DFM review, change the fab profile, or apply the fixes.

0.11 mm against at least 0.127 mm
Violation · usually caught by CAD DRC
Copper that close can bridge during etching or plating.
0.10 mm against at least 0.15 mm
Violation · usually caught by CAD DRC
Drill wander can break a thin ring and leave an open via.
0.20 mm against at least 0.3 mm
Violation · usually caught by CAD DRC
Routing and V-score tolerance can expose or short edge copper.
overlaps by 0.20 mm against at least 0.15 mm
Violation · usually caught by CAD DRC
Ink on a pad ruins solderability, so the fab clips the text or rejects.
0.09 mm against at least 0.1 mm
Check off · usually caught by the fab's DFM review
A thin mask strip between pads peels off, and then solder bridges.
35° against at least 45°
Check off · usually caught by the fab's DFM review
Etchant pools in an acute wedge and over-etches or leaves residue.
solid connection against thermal relief spokes
Check off · usually caught by the fab's DFM review
A pad on a solid pour heats late and tombstones small parts.

Rules to check against

4 violations: 4 that CAD DRC would catch with these numbers and 0 that usually need the fab's DFM review or an assembly check. Profile numbers are illustrative; always use your fab's current capability sheet.

In practice

Practice

Read a capability sheet and export the right files

You have the fab's capability sheet and the values from your own board. Decide which design values break the sheet and what the smallest fix is.

Parameter	Fab capability (standard tier)	Your design
Trace / space	0.127 / 0.127 mm	0.15 / 0.10 mm at the TQFP escape
Via drill / pad	0.3 / 0.6 mm, ring 0.15 mm	0.3 / 0.5 mm
Mask web	0.10 mm	QFN, 0.5 mm pitch, 0.3 mm pads, 0.05 mm mask expansion each side
Copper to board edge	0.3 mm	Ground pour pulled back 0.2 mm
Silkscreen	0.15 mm line, 1.0 mm tall	0.1 mm line, 0.8 mm tall
Smallest drill	0.3 mm	0.25 mm thermal vias under a QFN

Then write the export checklist: which KiCad outputs go to the fab, which go to the assembler, and what you check before uploading.

Worked answer

Spacing 0.10 mm is below 0.127 mm, so widen the gap to 0.127 mm or more (0.15 mm is comfortable) or pay for the finer tier.
Via ring is (0.5 − 0.3) / 2 = 0.10 mm, below 0.15 mm. Use a 0.6 mm pad.
Mask web is 0.5 − 0.3 − 2 × 0.05 = 0.10 mm. It meets the sheet exactly, with no margin, so cut the expansion to 0.03 mm or the pad to 0.28 mm.
Copper to edge 0.2 mm is below 0.3 mm. Pull the pour back to 0.3 mm and set the same value in Board Setup, Constraints.
Silkscreen fails twice: a 0.1 mm line is under 0.15 mm and 0.8 mm text is under 1.0 mm. Use 1.0 mm text with a 0.15 mm stroke.
A 0.25 mm thermal via is under the 0.3 mm minimum drill. Use 0.3 mm vias or order the tier that allows 0.2 mm.

Export checklist, KiCad 9: run DRC with zero errors and fill the zones; File, Fabrication Outputs, Gerbers with F.Cu, B.Cu (and inner layers), F.Mask, B.Mask, F.Silkscreen, B.Silkscreen, F.Paste, B.Paste and Edge.Cuts, with the drill and place origin used consistently; generate the Excellon drill files; export the component placement file (CSV, millimetres, SMD only) and the BOM with supplier part numbers; zip the Gerbers and drills; open them in a Gerber viewer and confirm the outline is closed and the drills sit in the pads; upload, read every DFM warning, then check the assembler's placement preview for rotation and polarity.

Real-world scenario

Half the 0402s tombstone

A 40-board run comes back from a low-cost assembler with about half of the 60 0402 capacitors and LEDs on every board, 28 to 32 of them, standing on one end after reflow. The failures are not random: each tombstoned part has one pad tied to a large ground pour with a solid connection and the other pad on a 0.2 mm trace. Parts with matching copper on both pads are fine, and so are the 0603 and larger parts. The assembler's profile log shows a preheat ramp of 3.5 °C/s.

Symptoms

28 to 32 of the 60 0402 parts on each board stand on one end; 0603 and larger parts are fine
Every failed part has one pad on the ground pour and the other on a thin 0.2 mm trace
The end that is lifted off the board is always the one on the ground pour
The reflow log shows a preheat ramp of 3.5 °C/s with almost no soak

Interview questions

screenWhat is the difference between DRC and DFM?

DRC checks the layout against rules you or the fab set in the CAD tool: clearance, track width, drill size, annular ring and courtyards. It is geometry against numbers. DFM asks whether a factory can build the board reliably and cheaply, so it also considers process effects such as acid traps, mask slivers, thermal balance of pads, paste volume, fiducials and panelisation. A board can pass DRC and still tombstone or come back with opens. I put the fab's capability sheet into the DRC rules first, then run the fab's own DFM check before paying.

screenWhat files do you send to a fab and to an assembler?

The fab needs Gerber RS-274X files for each copper layer, solder mask, silkscreen, paste and the board outline, plus an Excellon drill file; some fabs accept a single IPC-2581 or ODB++ package instead. For assembly I add a bill of materials with manufacturer or supplier part numbers, a centroid file listing each reference designator's X, Y, rotation and side, and an assembly drawing with polarity marks. I open the Gerbers in a viewer before uploading, and I check the assembler's placement preview for rotation errors on polarised parts.

deepWalk me through a reflow profile for SAC305 and what goes wrong at each end.

Preheat brings the board up at no more than about 3 °C/s to 150 °C so the parts are not shocked. The soak from 150 to about 200 °C over 60 to 120 seconds activates the flux and evens out temperature between large and small parts. Then the board ramps through the 217 °C liquidus of SAC305 to a peak around 245 °C and spends 45 to 90 seconds above liquidus, long enough to wet but short enough to protect parts and limit intermetallic growth. Too cool or too short gives dull cold joints and poor wetting, while too hot or too long damages components and the laminate. Cooling quickly but no faster than about 6 °C/s, which would shock the parts, gives a fine-grained joint, while a very slow cool coarsens the grain and thickens the brittle intermetallic layer.

screenWhat is tombstoning and how do you prevent it?

Tombstoning is when a small chip, usually 0402 or smaller, stands on one end after reflow. It happens when the solder on one pad melts before the other, so surface tension pulls that end down and lifts the far end. The usual causes are unequal thermal mass between the pads, such as one pad on a pour, unequal pad size or paste volume, and a fast ramp. I prevent it with symmetric pads, thermal relief on any pad tied to a pour, balanced stencil apertures and a slower ramp with a soak.

deepHow do you decide the trace/space and drill sizes for a new board?

I start from the fab's capability page and pick the cheapest tier that fits, because tighter rules cost money and yield. My defaults are 0.2 mm track and space and a 0.3 mm drill with a 0.6 mm via pad, and I drop to the fab's minimum only locally, for example escaping a fine-pitch QFN. I leave 20 to 30 % margin over the minimum so normal process variation does not turn into scrap. Then I enter those numbers as design rules in the CAD tool so DRC enforces them while I route, and I confirm with the fab's DFM check before ordering.

deepWhat would DFM at compile time mean for AI-generated hardware designs?

It means treating manufacturability as a compiler pass instead of a review at the end. An AI system proposes geometry or a layout, and an automated checker applies the fab's rules, such as minimum wall thickness, drill sizes, clearances and bend radii. The violations go back to the generator as errors, and the loop runs until the design compiles with zero violations. For a PCB the same idea is a CI job that runs DRC with the fab's rules on every commit and fails the build on any violation. It moves the discovery of a 0.1 mm sliver from after the order to before a human ever sees the draft.

References and further reading

Where the ideas in this lesson come from, and what to read next. Books are the standard texts; papers are the original sources; standards are what employers work to.

Book
Clyde F. Coombs Jr. and Happy T. Holden (editors) (2016). Printed Circuits Handbook. McGraw-Hill, 7th edition.
Read: The fabrication and assembly chapters: imaging, etching, lamination, reflow.
Standard
IPC (2020). IPC-A-610H: Acceptability of Electronic Assemblies. IPC.
Read: The solder-joint acceptability criteria.
Standard
IPC (2010). IPC-7351B: Generic Requirements for Surface Mount Design and Land Pattern Standard. IPC.
Read: Why pad geometry decides tombstoning.

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Key terms

DRC (design rule check): A CAD check that tests the layout against numeric rules you set: clearance, track width, drill size, annular ring, courtyards. It knows geometry and the numbers you gave it, not the factory's process.
DFM (design for manufacturability): The practice and the checks that ask whether a factory can build the design repeatably, cheaply and at high yield. It covers effects DRC cannot see: acid traps, mask slivers, thermal balance, paste volume and panelisation.
Gerber (RS-274X): The standard 2-D vector format for PCB artwork, one file per copper, solder mask, silkscreen, paste and outline layer. Extended Gerber carries its aperture definitions inside the file.
Excellon drill file: The text format that lists drill sizes and hole coordinates, usually split into plated and non-plated holes. It is the companion to the Gerber set.
IPC-2581: A single XML file holding layers, drills, stack-up, netlist and bill of materials, intended to replace a zip of Gerbers and drill files.
Centroid (pick-and-place) file: A table giving each part's reference designator, X, Y, rotation and board side. The assembler's machine uses it to place components, and rotation conventions differ between CAD tools and assembly houses.
Annular ring: The ring of copper left around a drilled hole, (pad diameter minus drill diameter) / 2. Fabs usually ask for 0.15 mm or more because drill wander can break a thinner ring.
Solder mask web (sliver): The strip of mask left between two neighbouring pad openings. Below about 0.1 mm it can peel off in processing, and solder bridges become likely.
Acid trap: An acute-angle copper corner where etchant pools and over-etches, or where residue is trapped. Keep junction angles at 90° or more, or use 45° chamfers.
Tombstoning: A small chip standing on one end after reflow because the solder on one pad melted first and its surface tension lifted the part off the other pad.
Reflow profile: The temperature-versus-time curve a board sees in the oven: preheat, soak, a peak above the solder's liquidus, controlled cooling. For SAC305: liquidus 217 °C, peak about 245 °C, 45 to 90 s above liquidus.
Thermal relief: Narrow spokes that join a pad to a copper pour so the pad heats like its neighbours during soldering instead of dumping its heat into the plane.
Fiducial: A bare copper dot with an open mask area that the pick-and-place camera uses to find the board's true position. Three on each board or panel is typical.
AOI (automated optical inspection): Cameras compare each solder joint and component against a reference image to find missing, shifted, rotated, tombstoned or starved parts after reflow.