How chips are made: wafer fabrication

From sand to a finished wafer

Every chip is made from the same handful of unit processes: oxidation, deposition, lithography, etch, implantation, planarization and metallization. A fab strings them into a loop that runs hundreds of times on a 300 mm disc of silicon. Learn the loop and any process flow becomes readable.

From quartz to a 300 mm wafer

It starts with quartz sand (SiO₂), reduced with carbon in an arc furnace to metallurgical-grade silicon of about 98-99% purity. The Siemens process turns that into trichlorosilane, distills it, and deposits it back as electronic-grade polysilicon at 9 to 11 nines (99.9999999% or better). In Czochralski (CZ) growth the polysilicon is melted in a quartz crucible at about 1,420 °C (silicon melts at 1,414 °C), a seed crystal is dipped in and pulled upward while rotating, and the melt freezes onto it as a single crystal. A 300 mm ingot is 1-2 m long and weighs up to a few hundred kilograms; boron or phosphorus added to the melt sets its doping. Wire saws slice it into wafers 775 µm thick, which are lapped, etched and polished flat to a few nanometres. Five companies (Shin-Etsu, SUMCO, GlobalWafers, Siltronic and SK Siltron) make most of the world’s wafers.

The cleanroom

One 0.1 µm particle on a critical layer can kill a die. Ordinary room air carries about 35 million particles of 0.5 µm or larger per cubic metre; the air around exposed wafers inside a modern tool meets ISO Class 1-3, at most 1,000 particles of 0.1 µm or larger per cubic metre. Wafers travel 25 at a time in sealed FOUPs (front-opening unified pods) carried by overhead robots, so people rarely touch them. Lithography bays use yellow light because resist reacts to blue and ultraviolet, and rinses use ultrapure water at 18.2 MΩ·cm.

The unit processes

Oxidation. Heating silicon to 800-1,200 °C in oxygen or steam grows SiO₂. At 1,000 °C, dry oxygen grows about 50 nm in an hour and steam about 380 nm. Roughly 44% of the oxide’s thickness comes from consumed silicon.
Deposition. CVD reacts gases on the surface to build oxide, nitride or polysilicon. PVD (sputtering) knocks metal atoms off a target for barriers and seed layers. ALD builds a film one self-limiting layer at a time, about 0.1 nm per cycle, which is how the 1-2 nm hafnium-oxide gate dielectric is made.
Photolithography. Spin on resist, expose it through a reticle imaged at 4× reduction, and develop it. Resolution is about k₁·λ/NA. DUV immersion scanners use 193 nm ArF laser light with water under the lens (NA 1.35) and print about 38 nm half-pitch per exposure; tighter pitches need multiple patterning. EUV uses 13.5 nm light from tin droplets hit by a CO₂ laser 50,000 times a second, reflected by mirrors in vacuum, and prints about 13 nm half-pitch. ASML is the only EUV supplier, at about $200 million per scanner (about $380 million for High-NA).
Etch. Wet etching in liquids such as hydrofluoric acid is selective but isotropic, so it undercuts the mask. Plasma (dry) etching uses ions and radicals to cut straight down, making vertical trenches, contacts and the 3D NAND holes that are more than 50 times deeper than they are wide.
Ion implantation. Boron, phosphorus or arsenic ions are fired in at keV to MeV energies, with doses from 10¹¹ to 10¹⁶ per cm². Energy sets depth; dose sets doping. An anneal, a one-second spike near 1,000-1,050 °C or a millisecond laser flash, repairs the lattice and activates the dopant.
CMP. Chemical mechanical planarization presses the wafer onto a rotating pad with abrasive slurry and flattens it to nanometres, because an exposure stays in focus over only about 100 nm of height.
Metallization. Since IBM introduced copper wiring in 1997, logic chips use the damascene process: etch trenches and vias in a low-k dielectric, line them with a few nanometres of TaN/Ta, electroplate copper and polish off the excess. Copper cannot be plasma-etched cleanly, so it is inlaid. A modern chip has 10-15 or more metal layers, from 20-40 nm pitch at the bottom to micrometre-thick power layers at the top.

A finished transistor and its wiring stack (schematic, not to scale). Wires get wider and thicker going up: the bottom levels are tens of nanometres wide, the top levels are micrometres thick and carry power to the bumps.

FEOL, BEOL and the loop

The front end of line (FEOL) builds transistors in the silicon: trench isolation, wells, the gate stack, spacers, source and drain, and silicide. The middle of line adds tungsten or cobalt contacts, and the back end of line (BEOL) stacks the copper wiring. The split is set by temperature: once copper and fragile low-k dielectric are on the wafer, everything must stay below about 400 °C, so all hot steps happen first. Patterning one layer is a loop: deposit or grow a film, coat, expose, develop, etch or implant, strip, clean and inspect. A leading-edge flow repeats it for 60 or more mask layers, about 1,000 steps, and a wafer spends roughly three months in the fab.

Yield and cost

Fabs track defect density D₀, the number of killer defects per cm². The simplest yield model is Poisson: Y = e^−A·D₀ for die area A. A mature process runs at roughly 0.05-0.1 defects per cm², so a 1 cm² die yields about 90%, but a 6 cm² GPU-class die at the same D₀ yields only 55%. That exponential penalty is why big chips carry spare memory rows and why the industry is moving to chiplets. Inspection tools from KLA and Applied Materials scan wafers after critical steps, and yield engineers match wafer-map signatures to the tool that caused them. None of it is cheap: a leading-edge fab costs more than $20 billion, and TSMC has committed $165 billion to its Arizona site.

Interactive: run one patterning loop

Patterning loop on a wafer cross-section

Step through one full loop: oxidize, coat, expose, develop, etch, strip, implant and metallize. Auto-play cycles through all nine steps.

Step 1 / 9

Bare wafer

A 300 mm p-type wafer, 775 µm thick, boron-doped to about 10 Ω·cm and polished flat to a few nanometres. Only the top few micrometres will ever hold transistors.

Tool: Wafer makers: Shin-Etsu, SUMCO, GlobalWafers, Siltronic, SK Siltron

Each step animates once when you arrive; reduced-motion settings show the end state immediately.

In practice

Practice

Dies per wafer and yield for a 100 mm² die

Your 10 mm × 10 mm (100 mm²) die runs on 300 mm wafers with a 3 mm edge exclusion. The process sits at D₀ = 0.1 defects/cm². Estimate (1) dies per wafer, (2) Poisson yield, (3) good dies per wafer. Then repeat for a 600 mm² GPU-class die.

text

Dies per wafer: DPW ≈ π·(d/2)²/S − π·d/√(2·S)
  full 300 mm:   π·150²/100 − π·300/√200 = 706.9 − 66.6 ≈ 640
  d = 294 mm:    π·147²/100 − π·294/√200 = 678.9 − 65.3 ≈ 614   → about 600

Yield (Poisson): A = 100 mm² = 1.0 cm²
  Y = exp(−A·D0) = exp(−1.0 × 0.1) = 0.905   → about 90%

Good dies ≈ 614 × 0.905 ≈ 555 per wafer

Same wafer, 600 mm² die (A = 6 cm²):
  DPW ≈ π·147²/600 − π·294/√1200 = 113.1 − 26.7 ≈ 86
  Y   = exp(−0.6) = 0.55
  Good dies ≈ 86 × 0.55 ≈ 47  (6× the area, but 12× fewer good dies)

The second term of the dies-per-wafer formula counts partial dies lost around the edge. Real planners also subtract scribe lanes (50-100 µm wide) and test-structure sites, but the estimate is usually within a few percent.

Real-world scenario

Yield drops after a CMP pad change

A 300 mm fab runs a 28 nm process at a steady 92% sort yield on a 1 cm² automotive microcontroller. On Monday the copper CMP tool that polishes metal 2 gets its scheduled pad replacement. By Thursday, sort yield on lots that went through that tool has fallen to 81%, and the yield engineer on call is asked to find out why before more wafers are scrapped.

Symptoms

Sort yield on affected lots falls from 92% to 81%, while lots polished on the sister CMP tool stay at 92%.
Wafer maps show failing dies in long arcs and lines that cross die boundaries instead of random single dies.
Electrical failures are metal-2 shorts and opens, and inline brightfield inspection after M2 CMP shows defect counts up 4×, classified as scratches.

Interview questions

screenWalk me through the steps used to pattern one layer.

First you deposit or grow the film you want to pattern, then spin on photoresist and bake it. The scanner exposes the resist through a reticle, and in a positive resist the developer dissolves the exposed areas. A plasma etch transfers that opening into the film, then the resist is stripped and the wafer is cleaned and inspected. That loop, with implants, depositions and CMP in between, repeats for every mask layer, which is 60 or more times on a leading-edge chip.

screenWhat is the difference between DUV immersion and EUV lithography?

DUV immersion uses 193 nm light from an ArF excimer laser, with water between the lens and the wafer to reach a numerical aperture of 1.35, which prints about 38-40 nm half-pitch in one exposure. Anything tighter needs multiple patterning, which adds masks, steps and overlay error. EUV uses 13.5 nm light made by hitting tin droplets with a CO2 laser, and because almost everything absorbs it, the optics are multilayer mirrors in vacuum. One EUV exposure can replace three or four DUV exposures on critical layers, which is why 7 nm-class nodes and below adopted it despite each scanner costing about $200 million.

screenWhat do FEOL and BEOL mean, and why does the split matter?

FEOL, front end of line, builds the transistors in the silicon: isolation, wells, gate stack, source and drain. BEOL, back end of line, builds the copper wiring and low-k dielectric layers on top, often 10 to 15 or more levels. The split is mostly about thermal budget: once copper and low-k films are on the wafer, everything must stay below about 400 °C, so all high-temperature anneals must be finished in the FEOL. The two halves also use different tools and different engineering teams.

deepYield on a large die is poor. How would you estimate it and what could you change?

I would start with the Poisson model, Y = exp(−A·D0): a 1 cm² die at 0.1 defects per cm² yields about 90%, but a 6 cm² die at the same defect density yields only about 55%. To improve it, I can lower D0 by tracing defect sources with inline inspection and wafer-map signatures. I can make defects non-fatal with redundancy, such as spare SRAM rows and columns repaired by fuses. Or I can split the design into chiplets, test each small die, and assemble only known good dies, which is exactly why AMD moved its server CPUs to chiplets.

deepWhy does an advanced process need CMP, and what can go wrong with it?

A lithography exposure only stays in focus over roughly 100 nm of height for immersion DUV, and less for EUV, so the wafer must be flat before every critical layer. CMP flattens oxide after trench isolation and removes the tungsten and copper overburden in damascene steps, leaving inlaid lines. Its failure modes are dishing of wide copper lines, erosion of dense arrays, scratches from slurry agglomerates or a badly conditioned pad, and leftover slurry particles. Designers help by following dummy-fill rules that keep metal density in a window, roughly 20% to 80%, so the polish removes material evenly.

Quiz

References and further reading

Where the ideas in this lesson come from, and what to read next. Books are the standard texts; papers are the original sources; standards are what employers work to.

Book
James D. Plummer, Michael D. Deal and Peter B. Griffin (2000). Silicon VLSI Technology: Fundamentals, Practice and Modeling. Prentice Hall.
Read: One chapter per unit process: oxidation, lithography, etch, implant, deposition.
Book
Stephen A. Campbell (2013). Fabrication Engineering at the Micro- and Nanoscale. Oxford University Press, 4th edition.
Read: The lithography and etch chapters, which are more practical.
Paperfree online
Gordon E. Moore (1965). Cramming More Components onto Integrated Circuits. Electronics 38(8), 114-117.
Read: Four pages; notice it is about cost per component, not speed.