Packaging and test · Hardware Academy

From a finished wafer to a part you can solder

A finished wafer is not a product yet. Each die still needs a tested, protected body with connections a circuit board can use and a path for its heat. Packaging and test cost from a few cents for a simple SOIC to hundreds of dollars for an AI accelerator, and today they decide as much about performance as the transistors do.

Sort, thin, dice and attach

Wafer sort (probe) comes first. A probe card with thousands of fine needles lands on each die’s pads, and automatic test equipment (ATE) from Advantest or Teradyne runs a short electrical test, storing a pass or fail bin for every die in a wafer map. Test structures in the scribe lines are measured too, giving the fab sheet resistance and threshold voltage for each lot. The wafer is then back-ground from 775 µm to 50-200 µm, mounted on tape and diced with a diamond blade or a laser. The blade’s kerf is about 20-30 µm wide, cut inside a dicing street (scribe lane) of about 50-100 µm. Only good dies are picked. Die attach glues each one to a lead frame or substrate with silver-filled epoxy, solder, or sintered silver for power devices.

Wire bond or flip chip

Wire bonding welds 15-50 µm gold or copper wires from pads on the die’s edge to the leads, one wire at a time at more than ten wires per second. It is cheap and flexible, but connections are limited to the perimeter and each millimetre of wire adds about 1 nH of inductance. Flip chip turns the die face down onto an array of solder bumps (C4 bumps at about 150-200 µm pitch) or copper pillars (40-80 µm pitch) spread over its whole area. That gives thousands of short, low-inductance connections and lets heat leave through the back of the die. An epoxy underfill fills the gap so the bumps survive thermal cycling.

Package families

Package	Pitch	Connections	Typical θJA	Where you see it
DIP (dual in-line)	2.54 mm	8-64	≈80-100 °C/W	Through-hole, breadboards, legacy parts
SOIC (small outline)	1.27 mm	8-28	≈100-160 °C/W	Op-amps, gate drivers, interface chips
QFN (quad flat no-lead)	0.4-0.65 mm	8-100	≈25-50 °C/W	Microcontrollers, regulators, RF
BGA (ball grid array)	0.4-1.27 mm	100-5,000+	≈10-25 °C/W	FPGAs, SoCs, GPUs
CSP / WLCSP (chip scale)	0.35-0.5 mm	4-400	≈50-100 °C/W	Phones and wearables

A chip-scale package is at most about 1.2× the die area; a wafer-level CSP puts solder balls directly on the die. The θJA column is for JEDEC test boards, so treat it as a starting point.

Flip-chip BGA cross-section. The die sits face down on C4 bumps in underfill; the substrate fans the bumps out to 1 mm-pitch balls. Most heat goes up through the lid into the heat sink; some goes down into the PCB.

2.5D, 3D, chiplets and HBM

In 2.5D packaging, dies sit side by side on a silicon interposer that carries fine wiring and through-silicon vias (TSVs). NVIDIA’s H100 places its 814 mm² GPU next to stacks of HBM on TSMC’s CoWoS interposer. HBM (high-bandwidth memory) is itself 3D: 8-12 DRAM dies, thinned and stacked with TSVs, exposing a 1024-bit interface for about 0.8-1.2 TB/s per stack. True 3D stacking bonds dies face to face; AMD’s 3D V-Cache hybrid-bonds a 64 MB SRAM die onto a CPU die at 9 µm pitch. Chiplets split one design into smaller dies: AMD’s EPYC Genoa combines up to 12 CPU dies on 5 nm with one I/O die on 6 nm, and the UCIe standard (2022) defines the die-to-die link. The reasons are yield (small dies yield exponentially better), the reticle limit of 26 × 33 mm (858 mm²) per die, and freedom to build each function on its best process.

The thermal path

Every watt has to reach the air. Datasheets model this as a chain of thermal resistances: Tj = Ta + P·θJA, where θJA in °C/W lumps junction-to-case, case-to-board and board-to-air. It is measured on a standard 4-layer JEDEC board (JESD51-7), so a small two-layer board can do much worse. A large flip-chip BGA with a lid has a junction-to-case resistance of only 0.1-0.3 °C/W, so the heat sink dominates. Commercial silicon is usually limited to a 125 °C junction, and many automotive parts to 150 °C.

Final test, burn-in and reliability

After assembly, final test runs every part on ATE, often at several temperatures (−40, 25 and 125 °C for automotive), and sorts it into speed and quality bins. Burn-in runs parts hot at raised voltage for hours to remove infant-mortality failures, the falling left edge of the bathtub curve. Qualification adds stress tests: 1,000 hours of high-temperature operating life (HTOL) at 125 °C, 1,000 temperature cycles from −55 °C to 125 °C, and humidity tests such as HAST. Two wear-out mechanisms dominate. Electromigration is electron current slowly dragging metal atoms out of lines and bumps; Black’s equation puts lifetime proportional to J⁻² and falling exponentially with temperature. Thermal-cycling fatigue cracks solder joints because silicon expands 2.6 ppm/°C and FR-4 about 14-17 ppm/°C.

Why packaging is the frontier

In 2023 and 2024 the bottleneck for AI accelerators was not wafers but TSMC’s CoWoS packaging capacity, which TSMC roughly doubled in a year. Hybrid bonding below 10 µm pitch, glass-core substrates (announced by Intel in 2023) and co-packaged optics are where much of the next decade’s gains will come from.

Interactive: take a package apart

Exploded package: flip-chip BGA vs QFN

Side view of the same layers. Pull them apart with the slider.

Heat spreader (lid). Nickel-plated copper lid that spreads heat toward the heat sink and protects the die during assembly.
Thermal interface (TIM1). Indium solder or a polymer gel that fills the microscopic gap between the die back and the lid.
Silicon die (face down). The active side and metal stack face the bumps, so heat leaves through the bare back of the die.
Bumps + underfill. C4 solder bumps or copper pillars under the whole die, locked in an epoxy underfill that shares the thermal-expansion strain.
Package substrate. Organic build-up laminate about 1 mm thick whose copper layers fan out from about 150 µm bump pitch to 1 mm ball pitch.
Solder balls. SAC305 solder balls about 0.5 mm across at 1.0 mm pitch, reflowed onto matching pads on the PCB.

Package

Explode60%

Flip chip: heat goes up through the die back, TIM and lid into a heat sink; signals go down through bumps, substrate and balls.

In practice

Practice

Will this regulator overheat?

A linear regulator dissipates 1.5 W in a QFN with θJA = 40 °C/W (JEDEC board). The enclosure reaches 50 °C and the part is rated for a 125 °C junction. (1) Find Tj. (2) What is the maximum power if you keep a 10 °C guard band? (3) A thermocouple on the package top reads 104 °C and the datasheet gives ΨJT = 2 °C/W. What is the real junction temperature?

text

(1) Tj = Ta + P·θJA = 50 + 1.5 × 40 = 110 °C
    Under 125 °C, but only 15 °C of margin: OK with little margin.

(2) Keep Tj ≤ 125 − 10 = 115 °C:
    P_max = (115 − 50) / 40 = 1.63 W

(3) Tj ≈ T_top + ΨJT·P = 104 + 2 × 1.5 = 107 °C
    Your board beats the JEDEC board (θJA ≈ (107 − 50)/1.5 = 38 °C/W).

Fixes if margin is too thin: more copper and 6-9 thermal vias under the
exposed pad, a package with lower θJA, or a buck converter instead of the LDO.

ΨJT (junction-to-top characterization parameter) is not a thermal resistance, because most heat does not leave through the top; it is a calibration factor for turning a case measurement into a junction estimate.

Real-world scenario

QFN pins open after reflow at a new contract manufacturer

A motor-controller board uses a 5 × 5 mm, 32-pin QFN gate driver with a 3.5 × 3.5 mm exposed thermal pad and nine thermal vias. The design moves to a new contract manufacturer with a freshly cut stencil. On the first 2,000 boards, 4% fail end-of-line test with driver faults, and two field units come back after a week of thermal cycling.

Symptoms

Failing boards show one or two QFN perimeter pins open; pressing on the package makes the fault disappear.
X-ray shows 35-50% voiding in the thermal-pad joint and the package sitting visibly tilted, with some edge joints barely wetted.
Boards that pass run the driver about 20 °C hotter than boards from the previous manufacturer.

Interview questions

screenCompare wire bonding and flip chip.

Wire bonding connects pads on the edge of the die to the package with 15-50 µm gold or copper wires. It is cheap, mature and tolerant of die changes, but I/O is limited to the perimeter and each millimetre of wire adds about 1 nH of inductance. Flip chip turns the die face down onto an area array of bumps or copper pillars, so a big die can have thousands of short, low-inductance connections, and heat leaves through the back of the die into a lid. Most microcontrollers and analog parts are wire-bonded; CPUs, GPUs and high-speed networking chips are flip chip.

screenA regulator dissipates 1.5 W in a package with θJA = 40 °C/W at 50 °C ambient. Is it OK?

The junction temperature is Ta + P·θJA = 50 + 1.5 × 40 = 110 °C. That is under a typical 125 °C limit, but with only 15 °C of margin, and θJA was measured on a JEDEC board that may have more copper than mine. I would check the copper area and thermal vias under the exposed pad, look for a package with lower θJA, or cut the dissipation, for example by replacing an LDO with a buck converter.

screenWhat are chiplets and why is the industry moving to them?

A chiplet design splits one large chip into several smaller dies connected inside one package, such as AMD's EPYC with up to 12 CPU dies around one I/O die. Small dies yield far better because yield falls exponentially with area. Each function can use its best process, like CPU cores on 5 nm and I/O on 6 nm, and the total can exceed the 858 mm² reticle limit of a single die. The costs are die-to-die interface power and latency, harder packaging, and the need to test dies well enough that only known good dies get assembled.

deepWhy do solder joints fail under thermal cycling, and how do packages manage it?

Silicon expands about 2.6 ppm/°C and an FR-4 board about 14-17 ppm/°C, so every temperature swing shears the joints that connect them. Each cycle adds a little plastic strain and a crack grows until the joint opens; the Coffin-Manson relation says life drops steeply as the temperature swing grows. Underfill locks the die to the substrate so flip-chip bumps share the strain, and larger balls, corner glue or compliant substrates help BGAs. Qualification runs something like 1,000 cycles from −55 °C to 125 °C and then cross-sections joints to look for crack growth.

deepWhat is HBM, and why does an AI accelerator need advanced packaging?

HBM stacks 8 to 12 or more DRAM dies with through-silicon vias and exposes a 1024-bit interface per stack, giving roughly 0.8-1.2 TB/s per stack. A bus that wide needs thousands of wires at tens of micrometres pitch, which only a silicon interposer or bridge can carry, not a normal organic substrate or PCB. So a GPU like NVIDIA's H100 sits beside its HBM stacks on a TSMC CoWoS interposer. In 2023 and 2024 that packaging capacity, not wafer capacity, was the bottleneck on AI accelerator supply.

Quiz

References and further reading

Where the ideas in this lesson come from, and what to read next. Books are the standard texts; papers are the original sources; standards are what employers work to.

Book
Rao R. Tummala (2001). Fundamentals of Microsystems Packaging. McGraw-Hill.
Read: Wire bond versus flip chip, substrates and thermal resistance.
Book
Stephen A. Campbell (2013). Fabrication Engineering at the Micro- and Nanoscale. Oxford University Press, 4th edition.
Read: The packaging chapter for a compact overview.