PCB Design

PCB layout and stack-up

Layers, copper weight, vias, trace width and placement strategy.

Day 5 · 60 min

After this lesson

You can describe a 4-layer stack-up and when it beats 2 layers.
You can size a trace for a given current with IPC-2221.
You can plan placement and routing for a small mixed-signal board.

From a stack of layers to a board you can route

What a board is made of

A printed circuit board is a sandwich of copper and glass-reinforced epoxy. FR-4 is woven glass in flame-retardant epoxy, with a dielectric constant near 4.3 and a glass-transition temperature of 135 to 170 °C, and the standard finished thickness is 1.6 mm (63 mil). A core is fully cured FR-4 with copper foil on both faces. Prepreg is partly cured glass-epoxy sheet that melts in the press at about 180 °C and bonds the cores and outer foils together; common types are 1080 (about 0.07 mm), 2116 (0.12 mm) and 7628 (about 0.2 mm). Copper weight is quoted in ounces per square foot: 1 oz is 35 µm (1.37 mil), 0.5 oz is 17.5 µm and 2 oz is 70 µm, and finished outer layers are usually 1 oz with inner layers at 0.5 oz. On top sit the solder mask, about 20 µm of epoxy, green by default and opened over the pads, and the silkscreen legend, which must stay off the pads. The exposed copper gets a surface finish: HASL is cheap but domed, while ENIG, 3 to 6 µm of nickel under a thin gold flash, is flat and suits fine pitch and BGAs.

Two layers or four

A 2-layer board is two 35 µm copper layers on one 1.5 mm core: cheap, and fine for simple, slow circuits. Its weakness is the return path, because a top-layer signal is 1.5 mm from the nearest plane and its return current must find its own way home. A 4-layer board adds two inner layers. The classic order is signal, ground, power, signal (SIG/GND/PWR/SIG), with a thin prepreg of about 0.2 mm between the top layer and a solid ground plane. Return currents then flow directly under their signals, loop areas shrink, EMI and crosstalk fall, and a 0.35 mm top-layer trace over 0.21 mm of prepreg is a 50 Ω transmission line; the same trace on a 2-layer board would have to be about 3 mm wide. Use 2 layers for simple boards, and move to 4 once you have fast edges, USB or a noisy motor driver beside analog. Keep the stack symmetric about the core so the board does not bow in reflow.

Vias

A through via is a plated hole through every layer; the usual minimum is a 0.3 mm drill with a 0.6 mm pad, and it adds about 1 nH of inductance. A blind via joins an outer layer to an inner one, a buried via joins inner layers only, and a microvia is laser-drilled, about 0.1 mm, across one dielectric layer. These need sequential lamination and cost far more, so stay with through vias until density forces a change. A single via carries on the order of 1 A, so use several in parallel for power, and put a via beside a decoupling capacitor's pad instead of at the end of a long stub.

A common 4-layer, 1.6 mm stack-up with its dimensions, a through via with clearance holes in both planes, a blind via, and the 50 Ω microstrip that the thin top prepreg makes possible.

Footprints and placement first

A footprint is the copper pads, the mask openings and the courtyard for a part, and an IPC-7351 land pattern sizes the pads from the part's tolerances. Always compare it with the datasheet's recommended pattern, and print the board 1:1 and lay a real part on the paper. Placement decides how good the board can be, because routing only connects what placement left. Fix the outline, the mounting holes (an M3 screw needs a 3.2 mm hole and about 6 mm of keep-out for its head), connectors and keep-outs first, such as the antenna area of an ESP32 module, which must stay free of copper. Then place the parts that carry current or make noise, put decoupling capacitors at their pins, keep analog parts and sensors away from switching nodes, and align parts in a few orientations to help assembly.

Routing, widths and design rules

Route power and ground first, then the critical signals, then the rest. Trace width follows IPC-2221: the copper area is (I / (k · ΔT^0.44))^1/0.725 mil², with k = 0.048 for outer and 0.024 for inner layers, and the width is that area divided by 1.378 mil per ounce of copper. At a 10 °C rise in 1 oz outer copper this gives 12 mil for 1 A, 31 mil for 2 A and 54 mil for 3 A; an inner layer needs about 2.6 times as much and 2 oz copper halves the width. Set the fab's limits as design rules before you route: 6/6 mil (0.15 mm) trace and space, a 0.3 mm drill, a 0.15 mm annular ring and 0.3 mm from copper to the board edge. Clearance (the air gap) and creepage (the path along the surface) grow with voltage: IPC-2221B Table 6-1 (column B2, uncoated external conductors) allows 0.1 mm up to 30 V and 0.6 mm from 31 to 150 V, and mains boards need millimetres.

Thermal relief, outline and panels

Connect a pad to a pour through thermal relief spokes so soldering heat stays at the joint, which prevents cold joints and tombstoning, but connect high-current pads solidly. Stitching vias tie ground pours together, and thermal vias sit under an exposed pad. Draw the board outline on its own layer with rounded corners. For production the fab arranges boards in a panel, joined by V-score lines or by tabs with perforated mouse bites, and a 5 mm rail carries fiducials and tooling holes for the pick-and-place machine; keep copper and parts at least 0.5 mm from a V-score line.

Interactive: explode the stack-up

Exploded PCB stack-up

Pull the layers apart, then hover or tap a layer, or choose one from the Layer list, to read what it does. Switch between a 2-layer and a 4-layer board to see where the ground plane and the 50 Ω trace come from.

Board

Explode70 %Layer (top to bottom)

L1 · top copper (SIG)35 µm (1 oz)

Components and their short connections live here: 1 oz finished copper after plating. Routing on L1 runs 0.21 mm above the ground plane, so each signal's return current is right beside it, which is what keeps loops small.

The pale yellow via on this layer is a blind via: it joins L1 to L2 and stops there. The dark-ringed via goes right through the board.

Copper layers: 4
Copper plus dielectric: 1.59 mm
50 Ω trace on the top layer: 0.35 mm (14 mil)
Return path under L1: solid GND plane

Thicknesses are labelled in real units but drawn out of scale: at true scale the 35 µm copper would be a hairline next to a 1 mm core. The example stack-up follows a common 1.6 mm, 7628 prepreg, 4-layer fab build.

Interactive: how wide must the trace be?

Trace width calculator (IPC-2221)

Set the current, the temperature rise you can live with, the copper weight and the layer. See the width in mil and millimetres, how it compares with a signal trace, and what the copper costs in voltage drop.

Current3 AAllowed temperature rise10 °C

Copper weight

Layer

Trace width needed: 53.8 mil / 1.37 mm
Round up to a standard width: 60 mil / 1.52 mm
Rise at that width: +8.4 °C
Copper cross-section: 74.2 mil²
Resistance over 50 mm: 16.1 mΩ
Voltage drop at 3.0 A: 48.4 mV
Heat in the trace: 145 mW
A 10 mil trace at this current: +160 °C

Trace length (for resistance)50 mm

IPC-2221 is a rule of thumb for steady current in still air. IPC-2152 is more accurate because it accounts for nearby planes and board thickness; a copper pour does better than either chart, and an enclosure does worse. Resistance uses 1.72 × 10⁻⁸ Ω·m at 20 °C and rises about 0.4% per °C.

For a full-page version with a live board cross-section, open the trace-width lab.

In practice

Practice

Plan the placement order for the motor-driver board

The motor-driver board is 60 × 40 mm with four M3 holes. It carries a battery connector J1, an AMS1117 regulator U2 with C1 and C2, an ESP32 module U1 with C3 and C4, the TB6612FNG U3 with C5, C7 and C8, motor connectors J2 and J3, and the EN network R1, C6 and SW1. Put these in the order you would fix or place them and say why. Then give a trace width for each of these nets in 1 oz outer copper at a 10 °C rise: the VBAT feed to the driver (3 A at a stall), the motor outputs (1.2 A), the 3V3 rail (0.5 A).

Answer: show the worked solution

text

1  Outline, four M3 holes 3.5 mm from the corners, and keep-outs
   (no copper under the ESP32 antenna end, which overhangs the top edge)
2  Edge connectors: J1 on the left, J2 and J3 on the right edge near U3's outputs
3  U1 ESP32 module, antenna at the top edge
4  U3 TB6612FNG between U1 and the motor connectors, so the motor loop is short
5  C5 and C8 against U3's VM pins, C7 at its VCC pin
6  U2 next to J1, with C1 and C2 on its pins
7  C3 and C4 at U1's 3V3 pin, then R1, C6 and SW1 beside EN
8  Test points, fiducials and silkscreen

Widths (IPC-2221, 1 oz outer, 10 °C rise)
  VBAT feed to U3, 3 A:   53.8 mil calculated -> draw 60 mil (1.5 mm), or a pour
  motor outputs, 1.2 A:   15.2 mil calculated -> draw 25 mil (0.6 mm)
  3V3 rail, 0.5 A:        4.6 mil calculated  -> draw 15 to 20 mil for robustness
  logic signals:          8 to 10 mil over the ground pour

Connectors and mechanical constraints come first because they cannot move. The driver then goes next to its motor connectors and the regulator next to the battery entry, which keeps the high-current loops short before anything else competes for space. Decoupling capacitors come last in placement but first in importance: they must touch the pins they serve. For routing, do the VBAT feed and the motor ground first, as wide traces or pours, and give them a Motor net class of 1.5 mm so the router cannot choose less; 60 mil of 1 oz copper then rises only about 8 °C at 3 A. Finish with the ground pours and stitching vias.

Real-world scenario

The board browns under the motor driver

A 2-layer, 1 oz motor-driver board runs fine in light testing. At the first stall test, with both motors drawing about 3 A, the robot smells of hot varnish within a minute and the laminate under the driver turns brown. The motors also lose torque: the battery connector reads 7.2 V while the driver's VM pins read 6.8 V. The layout shows that the feed to the driver is a 10 mil (0.25 mm) trace, 50 mm long, because the autorouter treated it like any other net.

Symptoms

A burnt-varnish smell and visibly brown laminate along the trace to the VM pins after a minute at 3 A.
About 0.4 V is lost between the battery connector and the driver at 3 A, and the motors stall at lower torque than the datasheet promises.
A thermal camera shows the trace at about 185 °C while the driver chip is only warm.
The board passes ERC and DRC with no messages.

Interview questions

screenWhy would you choose a 4-layer board over a 2-layer board?

A 4-layer stack of signal, ground, power and signal gives every signal a solid, unbroken ground plane next to it, which shrinks the loop area of every current and lowers EMI and crosstalk. It also makes power distribution easier, because a plane or large pour feeds the whole board at low impedance. With about 0.2 mm of prepreg between the top layer and the ground plane, a 0.35 mm trace becomes a 50 Ω line, which a 2-layer board with a 1.5 mm gap cannot do without a trace about 3 mm wide. The cost is a prototype that is several times more expensive and a stack-up you must specify, so I use 2 layers for simple low-speed boards and move to 4 once there is an MCU with fast edges, USB or a noisy motor driver next to analog.

screenHow do you size a trace for 3 A?

I use IPC-2221, or IPC-2152 when accuracy matters, starting from a temperature-rise budget of 10 to 20 °C. For 3 A, a 10 °C rise and 1 oz copper on an outer layer the width is about 54 mil, 1.4 mm, and an inner layer needs about 2.6 times that. Going to 2 oz copper halves the width, and a copper pour is better still because it spreads the heat and costs no routing effort. Then I check the voltage drop, which for 50 mm of 1.4 mm trace is only about 18 mΩ, and the vias, since a 0.3 mm via carries on the order of 1 A, so a layer change needs several in parallel.

screenWhat are through, blind, buried and micro vias, and when do you use each?

A through via is drilled through the whole board and plated, the cheapest option and the default. A blind via joins an outer layer to one or more inner layers without reaching the other face, and a buried via joins inner layers only, so neither shows on both sides. A microvia is laser-drilled, about 0.1 mm across, and spans a single dielectric layer, which is how high-density boards escape fine-pitch BGAs. Blind, buried and micro vias need sequential lamination and cost much more, so I stay with through vias at a 0.3 mm drill and 0.6 mm pad unless pitch or density forces a change.

screenHASL or ENIG, and why?

HASL coats the pads with molten solder and levels them with hot air. It is cheap and robust, but the surface is uneven, which hurts fine-pitch parts below about 0.5 mm and BGAs. ENIG plates 3 to 6 µm of electroless nickel under a thin immersion gold flash of 0.05 to 0.1 µm, which is flat, keeps well on the shelf and suits fine pitch, at a higher cost and with a small risk of black-pad defects. For a prototype robot board with 0.65 mm pitch parts, lead-free HASL is usually fine, and I choose ENIG for fine pitch, BGAs or anything that needs flat pads.

deepWalk me through your placement and routing order for a mixed-signal board with a motor driver.

I start with the constraints: the board outline, mounting holes, connectors and keep-outs such as the antenna area. Then I place the power entry and the driver near the motor connectors so the high-current loops are short, the regulator close to the battery input, and the MCU with its decoupling capacitors at the pins, keeping analog and sensor parts on the far side from the noisy switching nodes. I route power and ground first with wide traces or pours, then the sensitive signals such as clocks and ADC inputs, then the rest, keeping signals over an unbroken plane. I finish with ground and power fills, stitching vias, silkscreen and a DRC pass, and then review the current loops and thermal paths once more.

deepWhat is thermal relief, and when do you turn it off?

Thermal relief connects a pad to a copper pour through a few narrow spokes, typically four spokes 0.25 to 0.3 mm wide. During soldering the pad then heats up quickly instead of dumping its heat into the whole pour, which prevents cold joints and tombstoning of small passives. The spokes add electrical and thermal resistance, so I switch relief off or use wide spokes on pads that carry high current, such as motor-driver supply pins and connectors. Under a QFN exposed pad, where heat has to leave the package, I use a solid connection with thermal vias, so I decide each case by asking whether the pad needs to solder easily or to conduct well.

References and further reading

Where the ideas in this lesson come from, and what to read next. Books are the standard texts; papers are the original sources; standards are what employers work to.

Standard
IPC (2012). IPC-2221B: Generic Standard on Printed Board Design. IPC.
Read: The conductor-width charts and clearance tables used by the calculator.
Standard
IPC (2009). IPC-2152: Standard for Determining Current Carrying Capacity in Printed Board Design. IPC.
Read: Read the introduction to see why its data supersedes the old charts.
Standard
IPC (2010). IPC-7351B: Generic Requirements for Surface Mount Design and Land Pattern Standard. IPC.
Read: Land-pattern geometry for footprints.
Book
Christopher T. Robertson (2004). Printed Circuit Board Designer's Reference: Basics. Prentice Hall.
Read: The stack-up and design-rule chapters.
Documentation
Altium Limited (2002). P-CAD 2002 PCB User's Guide. Altium, 620 pages.
Read: Chapter 3 (layers, placement, selection, properties) for layout concepts in an older tool.
Documentationfree online
David Haboud, Altium (2016). Getting Started with PCB Design. Altium tutorial, 29 pages.
Read: Pages 14-27: transferring to the PCB, placement, design rules, routing, 3D view.

← Previous Next: Power integrity, signal integrity and EMI →

Key terms

FR-4, core and prepreg: FR-4 is glass-woven epoxy laminate. A core is fully cured FR-4 with copper on both faces; prepreg is partly cured glass-epoxy sheet that melts and bonds the layers during lamination. A standard board is 1.6 mm thick.
Copper weight: Copper thickness quoted in ounces per square foot: 1 oz is 35 µm (1.37 mil), 0.5 oz is 17.5 µm and 2 oz is 70 µm. Outer layers are usually 1 oz finished and inner layers 0.5 oz.
Stack-up: The ordered list of copper and dielectric layers with their thicknesses. A 4-layer SIG/GND/PWR/SIG stack keeps a solid reference plane directly under each outer routing layer.
Solder mask and silkscreen: Mask is the roughly 20 µm epoxy coating (green by default) that keeps solder off everything except the pads. Silkscreen is the ink for designators and outlines, and it must stay off pads.
HASL and ENIG: Surface finishes. HASL is hot-air-levelled solder: cheap but uneven. ENIG is electroless nickel (3 to 6 µm) under a thin gold flash (0.05 to 0.1 µm): flat, long shelf life, suited to fine pitch and BGAs, at higher cost.
IPC-2221 trace width: A current-capacity rule: area = (I / (k · ΔT^0.44))^(1/0.725) in mil², with k = 0.048 outer and 0.024 inner. 3 A at a 10 °C rise needs about 54 mil (1.4 mm) in 1 oz outer copper.
Via types: A through via is drilled through every layer. A blind via joins an outer layer to an inner one, a buried via joins inner layers only, and a microvia is laser-drilled, about 0.1 mm, spanning one dielectric layer in HDI boards.
Clearance and creepage: Clearance is the shortest air gap between conductors; creepage is the shortest path along the surface. Both grow with voltage: IPC-2221B Table 6-1 (column B2, uncoated external conductors) allows 0.1 mm up to 30 V and 0.6 mm from 31 to 150 V, and mains needs millimetres.
Thermal relief: Narrow spokes that connect a pad to a copper pour so soldering heat is not drained away, which prevents cold joints and tombstoning. Pads that carry high current are connected solidly instead.
Design rules (6/6 mil): The minimum trace width and spacing (6 mil is 0.15 mm), drill (0.3 mm) and annular ring (0.15 mm) your fab builds reliably. Set them before routing so the design-rule check enforces them.